FM_NODE[1]
FM_NODE[2]
FM_NODE[3]
FM_NODE[4]
TO_NODE[0]
BYPASS[2]–
BYPASS[3]–
BYPASS[4]–
FM_NODE[0]
TO_NODE[1]
TO_NODE[2]
TO_NODE[3]
TO_NODE[4]
BYPASS[1]–
BYPASS[0]–
SD
EQU
BLL
TTL
BLL
EQU
TTL
BLL
EQU
TTL
BLL
EQU
TTL
BLL
EQU
TTL
TTL
SD
1
0
1
0
1
0
1
0
1
0
Figure 1. Block diagram of HDMP-0450.
HDMP-0450 Block Diagram
BLL OUTPUT
All TO_NODE[n]± high-speed
differential outputs are driven by
a Buffered Line Logic (BLL)
circuit that has on-chip source
termination, so no external bias
resistors are required. The BLL
outputs on the HDMP-0450 are of
equal strength and can drive in
lengthy FR-4 PCB trace.
Unused outputs should not be left
unconnected. Ideally, unused
outputs should have their
differential pins shorted together
with a short PCB trace. If longer
traces or transmission lines are
connected to the output pins, the
lines should be differentially
terminated with an appropriate
resistor. The value of the
termination resistor should match
the PCB trace differential
impedance.
EQU INPUT
All FM_NODE[n]± high-speed
differential inputs have an
Equalization (EQU) buffer to
offset the effects of skin loss and
dispersion on PCBs. An external
termination resistor is required
across all high-speed inputs. The
value of the termination resistor
should match the PCB trace
differential impedance.
Alternatively, instead of a single
resistor, two resistors in series,
with an AC ground between them,
can be connected differentially
across the FM_NODE[n]± inputs.
The latter configuration
attenuates high-frequency
common mode noise.
BYPASS[n]- INPUT
The active low BYPASS[n]- inputs
control the data flow through the
HDMP-0450. All BYPASS pins are
LVTTL and contain internal pull-
up circuitry. To bypass a port,
the appropriate BYPASS[n]- pin
should be connected to GND
through a 1 kΩ resistor.
Otherwise, the BYPASS[n]-inputs
should be left to float, as the
internal pull-up circuitry will
force them high.
SD OUTPUT
The Signal Detect (SD) block
detects if the incoming data on
FM_NODE[0]± is valid by
examining the differential
amplitude of that input. The
incoming data is considered
valid, and SD is driven high, as
long as the amplitude is greater
than 400 mV (differential peak-to-
peak). SD is driven low as long as
the amplitude of the input signal
is less than 100 mV (differential
peak-to-peak). When the ampli-
tude of the input signal is
between 100-400 mV (differential
peak-to-peak), the SD output is
undefined.
2
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
