Functional Pin Description
Table 4. Functional Pin Descriptions.
Pin
HCTL
2032/
2032-SC
Symbol
Description
HCTL
2022
V
V
1
1
Power Supply
DD
SS
18
5
12
3
Ground
CLK
CLK is a Schmitt-trigger input for the external clock signal.
CHA
15
16
14
13
10
NC
9
CHA , CHA , CHB , and CHB are Schmitt-trigger inputs that accept the outputs from
X Y X Y
X
CHA
a quadrature-encoded source, such as incremental optical shaft encoder. Two
channels, A and B, nominally 90 degrees out of phase, are required. CHA and CHB
X
Y
CHB
CHB
X
Y
X
st
nd
NC
are the 1 axis and CHA and CHB are the 2 axis.
Y Y
CHI
CHI
17
19
11
NC
CHI and CHI are Schmitt-trigger inputs that accept the outputs of Index channel
X Y
from an incremental optical shaft encoder.
X
Y
RSTNX
RSTNY
12
11
8
NC
This active low Schmitt-trigger input clears the internal position counter and the
position latch. It also resets the inhibit logic. RST / and RST / are asynchronous with
X Y
st
respect to any other input signals. RST / is to reset the 1 axis counter and RST / is
to reset the 2 axis counter.
X
Y
nd
OEN
7
5
This CMOS active low input enables the tri-state output buffers. The OE/, SEL1, and
SEL2 inputs are sampled by the internal inhibit logic on the falling edge of the clock to
control the loading of the internal position data latch.
SEL1
SEL2
6
26
4
17
These CMOS inputs directly controls which data byte from the position latch is
enabled into the 8-bit tri-state output buffer. As in OE/ above, SEL and SEL also
1 2
control the internal inhibit logic.
BYTE SELECTED
SEL1
SEL2
MSB
D4
2ND
3RD
LSB
D1
0
1
0
1
1
1
0
0
D3
D2
EN1
EN2
2
3
NC
NC
These CMOS control pins are set to high or low to activate the selected count mode
before the decoding begins.
Count Modes
EN1
EN2
4x
2x
1x
0
1
0
1
0
0
1
1
Illegal Mode
On
On
On
st
nd
st
X/Y
32
NC
Select the 1 or 2 axis data to be read. Low bit enables the 1 axis data, while high
nd
bit enables the 2 axis data.
CNTDEC 27
NC
NC
A pulse is presented on this LSTTL-compatible output when the quadrature decoder
X
st
CNTDEC 28
(4x/2x/1x) has detected a state transition. CNTDEC is for 1 axis and CNTDEC is
Y
X
Y
nd
for 2 axis.
U/Dx
U/Dy
8
9
6
NC
This LSTTL-compatible output allows the user to determine whether the IC is
counting up or down and is intended to be used with the CNTDEC and CNTCAS
outputs. The proper signal U (high level) or D/ (low level) will be present before the
rising edge of the CNTDEC and CNTCAS outputs.
5
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