6
Switching Specifications
Over recommended temperature (T
A
= -40°C to +85°C), V
CC
= 5 V, I
F
= 7.5 mA, unless otherwise
specified.
Parameter
Propagation Delay
Time to High
Output Level
Propagation Delay
Time to Low
Output Level
Pulse Width
Distortion
Propagation Delay
Skew
Output Rise Time
(10-90%)
Output Fall Time
(90-10%)
Common Mode
Transient
Immunity at
High Output
Level
Common Mode
Transient
Immunity at
Low Output
Level
Symbol
t
PLH
Device
Min.
20
Typ.* Max.
75
48
100
75
t
PHL
|t
PHL
-t
PLH
|
t
PSK
t
r
t
f
HCPL-2630/0630
|CM
H
|
HCPL-2631/0631
24
10
10,000
5,000 10,000
V/µs
25
50
100
3.5
35
40
ns
ns
ns
ns
ns
V
CM
= 10 V
V
CM
= 50 V
V
CM
= 1000 V
V
CM
= 10 V
V/µs
V
CM
= 50 V
V
CM
= 1000 V
V
O(MIN)
= 2 V,
R
L
= 350
Ω,
I
F
= 0 mA,
T
A
= 25°C
V
O(MAX)
= 0.8 V,
R
L
= 350
Ω,
I
F
= 7.5 mA
T
A
= 25°C
11
11
ns
ns
T
A
= 25°C
R
L
= 350
Ω
C
L
= 15 pF
7, 8, 9
10
3, 7
13
13,14
3
3
Units
ns
Test Conditions
T
A
= 25°C
Fig.
7, 8, 9
Note
3, 6
12
3, 8,
10
HCPL-4661/0661 10,000 15,000
HCPL-2630/0630
|CM
L
|
HCPL-2631/0631
10,000
5,000 10,000
12
3, 9,
10
HCPL-4661/0661 10,000 15,000
*All typical values are at V
CC
= 5 V, T
A
= 25°C.
Notes:
1. Bypassing of the power supply line is required with a 0.1
µF
ceramic disc capacitor adjacent to each optocoupler. Total lead
length between both ends of the capacitor and the isolator pins should not exceed 10 mm.
2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current
does not exceed 15 mA.
3. Each channel.
4. Measured between pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together.
5. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together.
6. The t
PLH
propagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the
rising edge of the output pulse.
7. The t
PHL
propagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the
falling edge of the output pulse.
8. CM
H
is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic
state (i.e., V
OUT
> 2.0 V).
9. CM
L
is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic
state (i.e., V
OUT
< 0.8 V).
10. For sinusoidal voltages, (|dV
CM
|/dt)
max
=
πf
CM
V
CM
(p-p).
11. As illustrated in Figure 15 the V
CC
and GND traces can be located between the input and the output leads to provide
additional noise immunity at the compromise of insulation capability.
12. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage
≥
3000 V
RMS
for 1 second
(Leakage detection current limit, I
I-O
≤
5
µA).
13. See application section; “Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew” for more information.
14. t
PSK
is equal to the worst case difference in t
PHL
and/or t
PLH
that will be seen between units at any given temperature within
the operating condition range.
15. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage
≥
6000 V
RMS
for 1 second
(Leakage detection current limit, I
I-O
≤
5
µA).
This option is valid for HCPL-2630/2631/4661 only.
16. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together.
17. Derate linearly above 80°C free-air temperature at a rate of 2.7 mW/°C for the SOIC-8 package.
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
