V
CC
INPUT
R
L
R
D
10%
90%
OUTPUT
INPUT
OUTPUT
t
t
s
d
t
t
f
r
Figure 12. Test circuit for response time.
V
CC
R
L
R
D
OUTPUT
Figure 13. Test circuit for frequency response.
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Copyright © 2004 Agilent Technologies, Inc.
Obsoletes 5989-0301EN
November 3, 2004
5989-1735EN
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