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A316J 参数 Datasheet PDF下载

A316J图片预览
型号: A316J
PDF下载: 下载PDF文件 查看货源
内容描述: 2.0安培门驱动光电耦合器与集成( VCE)去饱和检测和故障状态反馈 [2.0 Amp Gate Drive Optocoupler with Integrated (Vce) Desaturation Detection and Fault Status Feedback]
分类和应用: 光电驱动
文件页数/大小: 34 页 / 619 K
品牌: AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
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27  
gate control signal is a  
Local Shutdown, Local Reset  
HCPL-316J  
continuous PWM signal, the fault  
latch will always be reset by the  
next time the input signal goes  
high. This configuration protects  
the IGBT on a cycle-by-cycle  
basis and automatically resets  
before the next ‘on’ cycle. The  
fault outputs can be wire ‘OR’ed  
together to alert the  
microcontroller, but this signal  
would not be used for control  
purposes in this (Auto-Reset)  
configuration. When the  
1
2
3
4
5
6
7
8
V
V
V
As shown in Figure 70, the fault  
output of each HCPL-316J gate  
driver is polled separately, and  
the individual reset lines are  
asserted low independently to  
reset the motor controller after a  
fault condition.  
IN+  
IN-  
CC1  
+
µC  
GND1  
RESET  
FAULT  
Global-Shutdown, Global  
Reset  
As shown in Figure 71, when  
configured for inverting  
operation, the HCPL-316J can be  
configured to shutdown  
automatically in the event of a  
fault condition by tying the  
V
V
LED1+  
LED1-  
HCPL- 316J is configured for  
Auto-Reset, the guaranteed  
minimum FAULT signal pulse  
width is 3 µs.  
Figure 70. Local Shutdown, Local  
Reset Configuration.  
FAULT output to V . For high  
IN+  
HCPL-316J  
reliability drives, the open  
1
2
3
4
5
6
7
8
V
V
V
IN+  
IN-  
Resetting Following a Fault  
Condition  
To resume normal switching  
operation following a fault  
condition (FAULT output low),  
the RESET pin must first be  
asserted low in order to release  
the internal fault latch and reset  
the FAULT output (high). Prior to  
asserting the RESET pin low, the  
collector FAULT outputs of each  
HCPL-316J can be wire ‘OR’ed  
together on a common fault bus,  
forming a single fault bus for  
interfacing directly to the micro-  
controller. When any of the six  
gate drivers detects a fault, the  
fault output signal will disable all  
six HCPL-316J gate drivers  
simultaneously and thereby  
provide protection against further  
catastrophic failures.  
CC1  
+
µC  
GND1  
RESET  
FAULT  
V
V
LED1+  
LED1-  
CONNECT  
TO OTHER  
RESETS  
input (V ) switching signals must  
IN  
be configured for an output (V )  
OL  
CONNECT  
TO OTHER  
FAULTS  
low state. This can be handled  
directly by the microcontroller or  
by hardwiring to synchronize the  
RESET signal with the  
appropriate input signal. Figure  
73a shows how to connect the  
Auto-Reset  
As shown in Figure 72, when the  
Figure 71. Global-Shutdown, Global  
Reset Configuration.  
inverting V input is connected  
IN-  
to ground (non-inverting  
configuration), the HCPL-316J  
can be configured to reset  
automatically by connecting  
HCPL-316J  
RESET to the V  
signal for safe  
IN+  
1
2
3
4
5
6
7
8
V
V
V
IN+  
automatic reset in the non-  
inverting input configuration.  
Figure 73b shows how to  
IN-  
RESET to V  
. In this case, the  
IN+  
gate control signal is applied to  
the non-inverting input as well as  
the reset input to reset the fault  
latch every switching cycle.  
During normal operation of the  
IGBT, asserting the reset input  
low has no effect. Following a  
fault condition, the gate driver  
remains in the latched fault state  
until the gate control signal  
CC1  
configure the V /RESET signals  
IN+  
+
µC  
so that a RESET signal from the  
microcontroller causes the input  
to be in the “output-off” state.  
Similarly, Figures 73c and 73d  
show automatic RESET and  
microcontroller RESET safe  
configurations for the inverting  
input configuration.  
GND1  
RESET  
FAULT  
V
V
LED1+  
LED1-  
changes to the ‘gate low’ state  
and resets the fault latch. If the  
Figure 72. Auto-Reset Configuration.  
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