25
HCPL-316J
1
2
3
4
5
6
7
8
V
V
V
IN+
IN-
HCPL-316J
HCPL-316J
V
16
15
V
16
15
E
E
V
V
100 pF
LED2+
CC1
LED2+
+
–
µC
3.3
DESAT 14
DESAT 14
GND1
kΩ
100 Ω
D
DESAT
V
13
12
11
10
9
V
13
12
11
10
9
CC2
CC2
RESET
FAULT
V
C
V
C
V
V
OUT
OUT
R
R
g
g
V
V
LED1+
LED1-
330 pF
V
V
EE
EE
R
PULL-DOWN
V
V
EE
EE
Figure 65. Output Pull-Down Resistor.
Figure 66. DESAT Pin Protection.
Figure 67. FAULT Pin CMR Protection.
value of 15 kV/µs. The added
capacitance does not increase the
fault output delay when a
desaturation condition is
detected.
DESAT Pin Protection
Other Recommended
Components
The freewheeling of flyback
diodes connected across the
IGBTs can have large
The application circuit in Figure
62 includes an output pull-down
resistor, a DESAT pin protection
resistor, a FAULT pin capacitor
(330 pF), and a FAULT pin pull-
up resistor.
instantaneous forward voltage
transients which greatly exceed
the nominal forward voltage of
the diode. This may result in a
large negative voltage spike on
the DESAT pin which will draw
substantial current out of the IC if
protection is not used. To limit
this current to levels that will not
damage the IC, a 100 ohm
resistor should be inserted in
series with the DESAT diode. The
added resistance will not alter the
DESAT threshold or the DESAT
blanking time.
Pull-up Resistor on FAULT Pin
The FAULT pin is an open-
collector output and therefore
requires a pull-up resistor to
provide a high-level signal.
Output Pull-Down Resistor
During the output high transition,
the output voltage rapidly rises to
Driving with Standard CMOS/
TTL for High CMR
within 3 diode drops of V
. If
CC2
the output current then drops to
zero due to a capacitive load, the
output voltage will slowly rise
Capacitive coupling from the
isolated high voltage circuitry to
the input referred circuitry is the
primary CMR limitation. This
coupling must be accounted for
to achieve high CMR perform-
from roughly V -3(V ) to V
CC2
BE
CC2
within a period of several
microseconds. To limit the output
voltage to V -3(V ), a pull-
CC2
BE
Capacitor on FAULT Pin for
High CMR
ance. The input pins V
and
IN+
down resistor between the output
V
IN-
must have active drive
and V is recommended to sink
EE
Rapid common mode transients
can affect the fault pin voltage
while the fault output is in the
high state. A 330 pF capacitor
(Fig. 66) should be connected
between the fault pin and ground
to achieve adequate CMOS noise
margins at the specified CMR
signals to prevent unwanted
switching of the output under
extreme common mode transient
conditions. Input drive circuits
that use pull-up or pull-down
resistors, such as open collector
configurations, should be
a static current of several 650 µA
while the output is high. Pull-
down resistor values are
dependent on the amount of
positive supply and can be
adjusted according to the
formula, R
=
pull-down
avoided. Standard CMOS or TTL
drive circuits are recommended.
[V -3 * (V )] / 650 µA.
CC2
BE
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