24
Behavioral Circuit
Schematic
signal input are both latched. The
fault output changes to an active
low state, and the signal LED is
forced off (output LOW). The
latched condition will persist until
the Reset pin is pulled low.
are never on at the same time. If
an undervoltage condition is
detected, the output will be
actively pulled low by the 50x
DMOS device, regardless of the
LED state. If an IGBT
desaturation fault is detected
while the signal LED is on, the
Fault signal will latch in the high
state. The triple darlington AND
the 50x DMOS device are
disabled, and a smaller 1x DMOS
pull-down device is activated to
slowly discharge the IGBT gate.
When the output drops below two
volts, the 50x DMOS device again
turns on, clamping the IGBT gate
firmly to Vee. The Fault signal
remains latched in the high state
until the signal LED turns off.
The functional behavior of the
HCPL-316J is represented by the
logic diagram in Figure 64 which
fully describes the interaction and
sequence of internal and external
signals in the HCPL-316J.
Output IC
Three internal signals control the
state of the driver output: the
state of the signal LED, as well as
the UVLO and Fault signals. If no
fault on the IGBT collector is
detected, and the supply voltage
is above the UVLO threshold, the
LED signal will control the driver
output state. The driver stage
logic includes an interlock to
ensure that the pull-up and pull-
down devices in the output stage
Input IC
In the normal switching mode, no
output fault has been detected,
and the low state of the fault
latch allows the input signals to
control the signal LED. The fault
output is in the open-collector
state, and the state of the Reset
pin does not affect the control of
the IGBT gate. When a fault is
detected, the FAULT output and
250 µA
V
(16ꢀ
E
DESAT (14ꢀ
+
V
V
(1ꢀ
(2ꢀ
IN+
IN–
–
LED
7 V
V
(3ꢀ
CC1
V
(13ꢀ
(12ꢀ
CC2
–
UVLO
GND (4ꢀ
DELAY
+
12 V
V
C
FAULT (6ꢀ
Q
V
(11ꢀ
OUT
R
S
50 x
RESET (5ꢀ
FAULT
V
(9,10ꢀ
EE
1 x
Figure 64. Behavioral Circuit Schematic.