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OR3T80-6PS240 参数 Datasheet PDF下载

OR3T80-6PS240图片预览
型号: OR3T80-6PS240
PDF下载: 下载PDF文件 查看货源
内容描述: 3C和3T现场可编程门阵列 [3C and 3T Field-Programmable Gate Arrays]
分类和应用: 现场可编程门阵列可编程逻辑
文件页数/大小: 210 页 / 4391 K
品牌: AGERE [ AGERE SYSTEMS ]
 浏览型号OR3T80-6PS240的Datasheet PDF文件第126页浏览型号OR3T80-6PS240的Datasheet PDF文件第127页浏览型号OR3T80-6PS240的Datasheet PDF文件第128页浏览型号OR3T80-6PS240的Datasheet PDF文件第129页浏览型号OR3T80-6PS240的Datasheet PDF文件第131页浏览型号OR3T80-6PS240的Datasheet PDF文件第132页浏览型号OR3T80-6PS240的Datasheet PDF文件第133页浏览型号OR3T80-6PS240的Datasheet PDF文件第134页  
Data Sheet  
June 1999  
ORCA Series 3C and 3T FPGAs  
Timing Characteristics (continued)  
Table 58. OR3C/Txxx Input to Fast Clock Setup/Hold Time (Pin-to-Pin)  
DD  
5
<
A
<
DD  
<
A
<
OR3Cxx Commercial: V = .0 V ± 5%, 0 °C  
T
70 °C; Industrial: V = 5.0 V ± 10%, –40 °C  
T
+85 °C.  
DD  
<
A
<
DD  
<
A
<
OR3Txxx Commercial: V = 3.0 V to 3.6 V, 0 °C  
T
70 °C; Industrial: V = 3.0 V to 3.6 V, 40 °C  
T
+85 °C.  
Speed  
Description  
Device  
Unit  
Max  
-4  
-5  
-6  
-7  
J
DD  
(T = 85 °C, V = min)  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Output Not on Same Side of Device As Input Clock (Fast Clock Delays Using ExpressCLK Inputs)  
Input to FCLK Setup Time (middle  
ECLK pin)  
ns  
ns  
ns  
ns  
ns  
OR3T20  
OR3T30  
OR3C/T55  
OR3C/T80  
OR3T125  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
Input to FCLK Setup Time (middle  
ECLK pin, delayed data input)  
ns  
ns  
ns  
ns  
ns  
OR3T20  
OR3T30  
OR3C/T55  
OR3C/T80  
OR3T125  
0.29  
0.14  
0.80  
0.74  
0.62  
0.50  
0.22  
0.58  
0.55  
0.51  
0.46  
0.33  
2.20  
2.17  
2.11  
2.06  
1.90  
Input to FCLK Setup Time (corner  
ECLK pin)  
ns  
ns  
ns  
ns  
ns  
OR3T20  
OR3T30  
OR3C/T55  
OR3C/T80  
OR3T125  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
Input to FCLK Setup Time (corner  
ECLK pin, delayed data input)  
ns  
ns  
ns  
ns  
ns  
OR3T20  
OR3T30  
OR3C/T55  
OR3C/T80  
OR3T125  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
0.00  
Input to FCLK Hold Time (middle  
ECLK pin)  
ns  
ns  
ns  
ns  
ns  
OR3T20  
OR3T30  
OR3C/T55  
OR3C/T80  
OR3T125  
6.33  
6.95  
4.29  
4.50  
4.97  
5.49  
6.36  
3.72  
3.80  
3.96  
4.15  
4.47  
3.27  
3.35  
3.52  
3.72  
4.05  
Notes:  
ORCA  
The pin-to-pin timing parameters in this table should be used instead of results reported by  
Foundry.  
The FCLK delays are for a fully routed clock tree that uses the ExpressCLK input into the fast clock network. It includes both the input buffer  
delay and the clock routing to the PFU CLK input. The delay will be reduced if any of the clock branches are not used.  
130  
Lucent Technologies Inc.  
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