Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Clock Manager (PCM) (continued)
PCM
INPUT
CLOCK
CHARGE PUMP
AND
LOW-PASS FILTER
PHASE
DETECTOR
0
EXPRESSCLK
PAD
FROM
ROUTING
PROGRAMMABLE
DIVIDER
1
2
S0
DIV0
0
S4
1
PROGRAMMABLE DELAY
LINES (32 TAPS)
3
1
S2
0
FEEDBACK
CLOCK
EXPRESSCLK
FEEDBACK
0
REGISTER 7
REGISTER 6
REGISTER 5
REGISTER 4
REGISTER 3
REGISTER 2
REGISTER 1
PROGRAMMABLE
1...7 1...7 1...7 1...7
1
S3
2
DIVIDER
DIV1
FROM
ROUTING
S5
S6
S7
S8
3
0
0
1
2
1
2
EXPRESSCLK
OUTPUT
S4
S4
PROGRAMMABLE
3
3
DIVIDER
DIV2
COMBINATORIAL
LOGIC
REGISTER 0
0
1
FPGA-PCM INTERFACE
SYSTEM CLOCK
OUTPUT
S10
2
3
0
5-5829(F)
Figure 46. PCM Functional Block Diagram
74
Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
