Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
The multiplied output is selected by setting register six,
bits [5:4] to 10 or 11 for ExpressCLK output and/or bits
[7:6] to 10 for system clock output. Note that when reg-
ister six, bits [5:4] are set to 11, the ExpressCLK output
is divided by DIV2, while the system clock cannot be
divided. The ExpressCLK divider is provided so that the
I/O clocking provided by the ExpressCLK can operate
slower than the internal system clock. This allows for
very fast internal processing while maintaining slower
interface speeds off-chip for improved noise and power
performance or to interoperate with slower devices in
the system.
Programmable Clock Manager (PCM)
(continued)
Clock Multiplication
An output clock that is a multiple (not necessarily an
integer multiple) of the input clock can be generated in
PLL mode. The multiplication ratio is programmed in
the division registers DIV0, DIV1, and DIV2. Note that
DIV2 applies only to the ExpressCLK output of the
PCM and any reference to DIV2 is implicitly 1 for the
system clock output of the PCM. The clock multiplica-
tion formulas when using ExpressCLK feedback are:
It is also necessary to configure the internal PCM oscil-
lator for operation in the proper frequency range.
Table 29 and Table 30 show the settings required for
register four for a given frequency range for Series 3C
and 3T devices. In addition, the acquisition time is
shown for each frequency range. This is the time that is
required for the PCM to acquire LOCK. The PCM oscil-
lator frequency range is chosen based on the desired
output frequency at the system clock output. If using
the ExpressCLK output, the equivalent system clock
frequency can be selected by multiplying the expected
ExpressCLK output frequency by the value for DIV2.
Choose the nominal frequency from the table that is
closest to the desired frequency, and use that value to
program register four. Minor adjustments to match the
exact input frequency are then performed automatically
by the PCM.
DIV1
ExpressCLK_OUT
INPUT_CLOCK
•
F
= F
DIV0
SYSTEM_CLOCK_OUT
ExpressCLK_OUT
• DIV2
F
= F
Where the values of DIV0, DIV1, and DIV2 range from
1 to 8.
The ExpressCLK multiplication range of output clock
frequencies is, therefore, from 1/8x up to 8x, with the
system clock range up to 8x the ExpressCLK frequency
or 64x the input clock frequency. If system clock feed-
back is used, the formulas are:
DIV1
SYSTEM_CLOCK_OUT
INPUT_CLOCK
•
F
= F
DIV0
SYSTEM_CLOCK
/DIV2
ExpressCLK_OUT
F
= F
The divider values, DIV0, DIV1, and DIV2 are pro-
grammed in registers zero, one, and two, respectively.
Lucent Technologies Inc.
77
AGERE [ AGERE SYSTEMS ]
