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OR3T55-6BA256 参数 Datasheet PDF下载

OR3T55-6BA256图片预览
型号: OR3T55-6BA256
PDF下载: 下载PDF文件 查看货源
内容描述: 3C和3T现场可编程门阵列 [3C and 3T Field-Programmable Gate Arrays]
分类和应用: 现场可编程门阵列可编程逻辑
文件页数/大小: 210 页 / 4391 K
品牌: AGERE [ AGERE SYSTEMS ]
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Data Sheet  
June 1999  
ORCA Series 3C and 3T FPGAs  
ExpressCLK that feeds the CLKCNTRL blocks on the  
two sides adjacent to the PCM, and one to the system  
clock spine network through general routing. Figure 45  
shows a high-level block diagram of the PCM.  
Programmable Clock Manager (PCM)  
The ORCA programmable clock manager (PCM) is a  
special function block that is used to modify or condi-  
tion clock signals for optimum system performance.  
Some of the functions that can be performed with the  
PCM are clock skew reduction (both internal and board  
level), duty-cycle adjustment, clock delay reduction,  
clock phase adjustment, and clock frequency multipli-  
cation/division. Due to the different capabilities required  
by customer application, each PCM contains both a  
PLL (phase-locked loop) and a DLL (delayed-locked  
loop) mode. By using PLC logic resources in conjunc-  
tion with the PCM, many other functions, such as fre-  
quency synthesis, are possible.  
Functionality of the PCM is programmed during opera-  
tion through a read/write interface internal to the FPGA  
array or via the configuration bit stream. The internal  
FPGA interface comprises write enable and read  
enable signals, a 3-bit address bus, an 8-bit input (to  
the PCM) data bus, and an 8-bit output data bus. There  
is also a PCM output signal, LOCK, that indicates a sta-  
ble output clock state. These signals are used to pro-  
gram a series of registers to configure the PCM  
functional core for the desired functionality.  
Operation of the PCM is divided into two modes, delay-  
locked loop (DLL) and phase-locked loop (PLL). Some  
operations can be performed by either mode and some  
are specific to a particular mode. These will be  
described in each individual mode section. In general,  
DLL mode is preferable to PLL mode for the same func-  
tion because it is less sensitive to input clock noise.  
There are two PCMs on each Series 3 device, one in  
the lower left corner and one in the upper right corner.  
Each can drive two different, but interrelated clock net-  
works inside the FPGA. Each PCM can take a clock  
input from the ExpressCLK pad in its corner or from  
general routing resources. There are also two input  
sources that provide feedback to the PCM from the  
PLC array. One of these is a dedicated corner Express-  
CLK feedback, and the other is from general routing.  
Each PCM sources two clock outputs, one to the corner  
In the discussions that follow, the duty cycle is the per-  
cent of the clock period during which the output clock is  
high.  
USER CONTROL SIGNALS  
PCM-FPGA  
INTERFACE  
CORNER EXPRESSCLK IN  
EXPRESSCLK OUT  
PCM CORE  
FUNCTIONS  
SYSTEM CLOCK OUT  
(TO GENERAL ROUTING)  
GENERAL CLOCKIN  
(FROM GENERAL ROUTING)  
FEEDBACK  
ExpressCLK  
FEEDBACK CLOCK  
FROM ROUTING  
5-5828(F)  
Figure 45. PCM Block Diagram  
72  
Lucent Technologies Inc.