Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
T
Index (continued)
Timing Characteristics
R
Asynchronous Peripheral Configuration Mode, 132
Boundry-Scan Timing, 119
Clock Timing, 119
Derating, 98
Description, 98
General Configuration Mode Timing, 129, 130
Master Parallel Configuration Mode, 131
Master Serial Configuration Mode, 130
Microprocessor Interface Configuration Timing, 137
PFU Timing, 100
RAM (see also FPGA Configuration), 85
Dual-port, 3, 10, 17
Single-port, 3, 10, 17
Recommended Operating Conditions, 95
Reconfiguration (see FPGA States of Operation)
Routing
3-Statable Bidirectional Buffers, 24
BIDI Routing, 24, 27
Clock (and Global CE and LSR) Routing, 30
Configurable Interconnect Points (CIPs), 24
Control Signal and Fast-Carry Routing, 27
Flexible Input Structure (FINS), 26
Inter-PLC Routing Resources, 28
Interquad Routing, 44
Intra-PLC Routing Resources, 26—27
Minimizing Routing Delay, 30
Overview, 5
PIO Timing, 108, 109, 110
PLC Timing, 107
Programmable Clock Manager Timing, 115
Readback Timing, 139
Slave Parallel Configuration Mode, 134
Slave Serial Configuration Mode, 133
SLIC Timing, 107
Tolerant I/O (see 5 V Tolerant I/O), 34
PFU Output Switching, 26
PIC Routing, 41—43
TS_ALL, 52 Twin-quad Architecture (see PFU), 1
PIC Interquad (MID) Routing, 46
PLC Routing, 26—32
U—Z
Programmable Corner Cell Routing, 45
SLIC Connectivity, 27
Zero-hold Inputs, 34—36
Switching Routing Segments (xSW), 26
S
SEL, 8, 10, 22
Softwired LUTs (SWLs),1, 6, 11, 12
(see also Look-Up Table Operating Modes)
Special Function Blocks
Boundary Scan, 60
Boundary-Scan Cells, 59
Boundary-Scan Timing, 60
Microprocessor Interface (MPI), 61—68
Programmable Clock Manager (PCM), 69—80
Single Function Blocks, 51
Clock Control (CLKCNTRL), 53
Global 3-State Control (TS_ALL), 52
Global Set/Reset (GSRN), 52
Internal Oscillator, 52
Readback Logic, 51
Start-Up Logic, 53
Start-Up (see FPGA States of Operation)
StopCLK, 1, 5, 53
(see also Special Function Blocks)
Subtractor (see LUT Operating Modes)
Supplemental Logic and Interconnect Cell (SLIC), 1,
18—21
System Clock (see Clock Distribution Network), 47
3-state, 3—4, 17—18, 34, 38, 45—46, 52, 56, 59, 82, 84
Lucent Technologies Inc.
209
AGERE [ AGERE SYSTEMS ]
