Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
E
Index
Electrical Characteristics, 97, 98
A
Error Checking (see FPGA Configuration)
ExpressCLK, 1, 6, 31, 34, 37, 39, 41, 43, 47—51,
70—74, 77—81
Absolute Maximum Ratings, 96
AND-OR-INVERT (AOI), 6
AND-OR-INVERT (AOI),1
(see also Supplemental Logic
Interconnect Cell (SLIC), 1
Architecture
(see also Clock distribution Network and
Programmable Clock Manager)
F
Overview, 6—9
ASWE, 9, 11, 15—17, 23, 33, 48
Fast Clock, 46—51, 54
(see Clock Distribution Network)
5 V Tolerant I/O 35
Flexible Input Structure (FINS) 1, 27, 32
(see also Routing)
FPGA Configuration, 87—94
Configuration Frame Format, 87
Configuration Modes, 89
Asynchronous Peripheral Mode, 91
Daisy-Chaining, 95
B
Bidirectional Buffers (BIDIs), 6, 19, 43, 83
(see also Routingand SLIC)
Bit Stream (see FPGA Configuration)
Bit Stream Error Checking, 88
(see also FPGA states of Operation)
Boundary Scan, 55
Master Parallel Mode, 89
Master Serial Mode, 90
Microprocessor Interface (MPI) Mode, 91
Slave Parallel Mode, 94
Slave Serial Mode, 94
(see Special Function Blocks)
C
Clock Control (CLKCNTRL), 50
(see also Clock Distribution Network and
Special Function Blocks)
Clock Distribution Network, 48–51
CLKCNTRL, 50
Data Format, 86
Data Frame, 86
Using ORCA Foundry to Generate RAM Data, 86
FPGA States of Operation
Configuration, 83
ExpressCLK, 48
Inputs, 51
Fast Clock, 48, 51
Global Control Signals, 48
In the PICs
Initialization, 82
Other Configuration Options, 85
Partial Reconfiguration, 85
Reconfiguration, 85
ExpressCLK, 50
System Clock, 50
Start-Up, 84
In the PLC Array
I
Fast Clock, 49
IEEE Standard, 1149.1 55, 59
Initialization (see FPGA States of Operation)
Input/Output Buffers
System Clock, 49
PFU Clock Sources, 48
Selecting Clock Input Pins, 51
System Clock, 48
Measurement Conditions, 138
Output Buffer Characteristics
OR3Cxx, 139
To the PLC Array
Fast Clock, 50
System Clock, 50
OR3Txxx, 141
Clock Enable (CE), 9, 11, 17, 23, 31, 48
Clock Multiplication (see PCM)
Comparator (see LUT Operating Modes)
Configuration (see FPGA States of Operation
or FPGA Configuration)
Control Inputs (see PICs, Inputs)
J
JTAG (see Boundry Scan)
D
Demultiplexing (see PICs, Input Demultiplexing), 38
Duty-Cycle Adjustment (see PCM)
Lucent Technologies Inc.
207
AGERE [ AGERE SYSTEMS ]
