ADXL36±
Data Sheet
FIFO Configuration
FIFO MODES
The FIFO is configured via Register 0x28 and Register 0x29.
Settings are described in detail in the FIFO Control Register
section.
The FIFO is a 512-sample memory buffer that can be used to
save power, unburden the host processor, and autonomously
record data.
FIFO Interrupts
The 512 FIFO samples can be allotted as either:
The FIFO can generate interrupts to indicate when samples are
available, when a specified number of samples has been collected,
and when the FIFO overflows and samples are lost. See the
Using FIFO Interrupts section for more information.
•
•
170 sample sets of concurrent 3-axis data; or
128 sample sets of concurrent 3-axis and temperature data
The FIFO operates in one of the four modes described in this
section.
Retrieving Data from FIFO
FIFO Disabled
FIFO data is read by issuing a FIFO read command, described
in the SPI Commands section. Data is formatted as a 16-bit
value as represented in Table 20.
When the FIFO is disabled, no data is stored in it and any data
already stored in it is cleared.
The FIFO is disabled by setting the FIFO_MODE bits in the
FIFO_CONTROL register (Address 0x28) to Binary Value 0b00.
When reading data, the least significant byte (Bits[B7:B0]) is
read first, followed by the most significant byte (Bits[B15:B8]).
Bits[B11:B0] represent the 12-bit, twos complement
acceleration or temperature data. Bits[B13:B12] are sign
extension bits, and Bits[B15:B14] indicate the type of data, as
listed in Table 20.
Oldest Saved Mode
In oldest saved mode, the FIFO accumulates data until it is full
and then stops. Additional data is collected only when space is
made available by reading samples out of the FIFO buffer. (This
mode of operation is sometimes referred to as “First N.”)
Table 20. FIFO Buffer Data Format
The FIFO is placed into oldest saved mode by setting the
FIFO_MODE bits in the FIFO_CONTROL register (Address
0x28) to Binary Value 0b01.
B15
B14
B13
B12
Sign
Extension
B11
B10
B9
B8
Data Type:
00: X-Axis
01: Y-Axis
10: Z-Axis
11: Temp
MSB
Data
Stream Mode
In stream mode, the FIFO always contains the most recent data.
The oldest sample is discarded when space is needed to make
room for a newer sample. (This mode of operation is sometimes
referred to as “Last N.”)
B7
B6
B5
B4
B3
B2
B1
B0
Data
LSB
Stream mode is useful for unburdening a host processor. The
processor can tend to other tasks while data is being collected in
the FIFO. When the FIFO fills to a certain number of samples
(specified by the FIFO_SAMPLES register along with the AH
bit in the FIFO_CONTROL register), it triggers a FIFO
watermark interrupt (if this interrupt is enabled). At this point,
the host processor can read the contents of the entire FIFO and
then return to its other tasks as the FIFO fills again.
Because the data format is 16-bit, the data must be read from
the FIFO two bytes at a time. When a multibyte read is
performed, the number of bytes read should always be an even
number. Multibyte reads of FIFO data can be performed with
no limit on the number of bytes read. If additional bytes are
read after the FIFO is empty, the data in the additional bytes are
read as 0x00.
The FIFO is placed into stream mode by setting the FIFO_MODE
bits in the FIFO_CONTROL register (Address 0x28) to Binary
Value 0b10.
As each sample set is acquired, it is written into the FIFO in the
following order:
•
•
•
•
X-axis
Y-axis
Z-axis
Temperature (optional)
Triggered Mode
In triggered mode, the FIFO saves samples surrounding an
activity detection event. The operation is similar to a one-time
run trigger on an oscilloscope. The number of samples to be
saved prior to the activity event is specified in FIFO_SAMPLES
(Register 0x29, along with the AH bit in the FIFO_CONTROL
register, Address 0x28).
This pattern repeats until the FIFO is full, at which point the
behavior depends on the FIFO mode (see the FIFO section). If
the FIFO has insufficient space for four data entries (or three
entries if temperature is not being stored), then an incomplete
sample set can be stored.
Place the FIFO into triggered mode by setting the FIFO_MODE
bits in the FIFO_CONTROL register (Address 0x28) to Binary
Value 0b11.
Rev. B | Page 38 of 44
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