ADXL36±
Data Sheet
POWER CONTROL REGISTER
Address: 0x2D, Reset: 0x00, Name: POWER_CTL
Table 18. Bit Descriptions for POWER_CTL
Bits
Bit Name
Reserved
EXT_CLK
Settings Description
Reset
0x0
Access
RW
7
Reserved.
6
External Clock. See the Using an External Clock section for additional details.
0x0
RW
1 = the accelerometer runs off the external clock provided on the INT1 pin.
Selects Power vs. Noise Tradeoff:
00 Normal operation (reset default).
01 Low noise mode.
[5:4]
LOW_NOISE
0x0
RW
10 Ultralow noise mode.
11 Reserved.
3
2
WAKEUP
Wake-Up Mode. See the Operating Modes section for a detailed
description of wake-up mode.
1 = the part operates in wake-up mode.
0x0
0x0
RW
RW
AUTOSLEEP
Autosleep. Activity and inactivity detection must be in linked mode or
loop mode (LINK/LOOP bits in ACT_INACT_CTL register) to enable
autosleep; otherwise, the bit is ignored. See the Motion Detection section
for details.
1 = autosleep is enabled, and the device enters wake-up mode
automatically upon detection of inactivity.
[1:0]
MEASURE
Selects Measurement Mode or Standby.
00 Standby.
0x0
RW
01 Reserved.
10 Measurement mode.
11 Reserved.
Rev. B | Page 34 of 44
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