ADXL36±
Data Sheet
Overrun
Alternate Functions of Interrupt Pins
The INT1 and INT2 pins can be configured for use as input
pins instead of for signaling interrupts. INT1 is used as an
external clock input when the EXT_CLK bit (Bit 6) in the
POWER_CTL register (Address 0x2D) is set. INT2 is used
as the trigger input for synchronized sampling when the
EXT_SAMPLE bit (Bit 3) in the FILTER_CTL register
(Address 0x2C) is set. One or both of these alternate functions
can be used concurrently; however, if an interrupt pin is used
for its alternate function, it cannot simultaneously be used for
its primary function, to signal interrupts.
The FIFO_OVERRUN bit (Bit 3) is set when the FIFO has
overrun or overflowed, such that new data replaces unread data.
This may indicate a full FIFO that has not yet been emptied or a
clocking error caused by a slow SPI transaction. If the FIFO is
configured to oldest saved mode, an overrun event indicates
that there is insufficient space available for a new sample.
The FIFO_OVERRUN bit is cleared automatically when the
contents of the FIFO are read. Likewise, when the FIFO is
disabled, the FIFO_OVERRUN bit is cleared.
USING SYNCHRONIZED DATA SAMPLING
External clocking and data synchronization are described in the
Applications Information section.
For applications that require a precisely timed acceleration
measurement, the ADXL362 features an option to synchronize
acceleration sampling to an external trigger. The EXT_SAMPLE
bit (Bit 3) in the FILTER_CTL Register (Address 0x2C) enables
this feature. When the EXT_SAMPLE bit is set to 1, the INT2
pin is automatically reconfigured for use as the sync trigger input.
Activity and Inactivity Interrupts
The ACT bit (Bit 4) and INACT bit (Bit 5) in the STATUS
register are set when activity and inactivity are detected,
respectively. Detection procedures and criteria are described in
the Motion Detection section.
When external triggering is enabled, it is up to the system
designer to ensure that the sampling frequency meets system
requirements. Sampling too infrequently causes aliasing. Noise
can be lowered by oversampling; however, sampling at too high
a frequency may not allow enough time for the accelerometer to
process the acceleration data and convert it to valid digital output.
Data Ready Interrupt
The DATA_READY bit (Bit 0) is set when new valid data is
available, and it is cleared when no new data is available.
The DATA_READY bit is not set while any of the data registers,
Address 0x08 to Address 0x0A and Address 0x0E to Address 0x15,
are being read. If DATA_READY = 0 prior to a register read
and new data becomes available during the register read,
DATA_READY remains at 0 until the read is complete and,
only then, is set to 1.
When Nyquist criteria are met, signal integrity is maintained.
An internal antialiasing filter is available in the ADXL362 and
can assist the system designer in maintaining signal integrity. To
prevent aliasing, set the filter bandwidth to a frequency no
greater than ½ the sampling rate. For example, when sampling
at 100 Hz, set the filter pole to no higher than 50 Hz. The filter
pole is set via the ODR bits in the FILTER_CTL register
(Address 0x2C). The filter bandwidth is set to ½ the ODR and is
set via these bits. Even though the ODR is ignored (as the data
rate is set by the external trigger), the filter is still applied at the
specified bandwidth.
If DATA_READY = 1 prior to a register read, it is cleared at the
start of the register read.
If DATA_READY = 1 prior to a register read and new data
becomes available during the register read, DATA_READY is
cleared to 0 at the start of the register read and remains at 0
throughout the read. When the read is complete, DATA_READY is
set to 1.
Because of internal timing requirements, the trigger signal
applied to pin INT2 must meet the following criteria:
Using FIFO Interrupts
FIFO Watermark
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The trigger signal is active high.
The FIFO_WATERMARK bit (Bit 2) is set when the number of
samples stored in the FIFO is equal to or exceeds the number speci-
fied in the FIFO_SAMPLES register (Address 0x29) together with
the AH bit in the FIFO_CONTROL register (Bit 3, Address 0x28).
The FIFO_WATERMARK bit is cleared automatically when
enough samples are read from the FIFO, such that the number
of samples remaining is lower than that specified.
The pulse width of the trigger signal must be at least 25 µs.
The trigger must be deasserted for at least 25 µs before it is
reasserted.
The maximum sampling frequency that is supported is
625 Hz (typical).
The minimum sampling frequency is set only by system
requirements. Samples need not be polled at any minimum
rate; however, if samples are polled at a rate lower than the
bandwidth set by the antialiasing filter, then aliasing may
occur.
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If the number of FIFO samples is set to 0, the FIFO watermark
interrupt is set. To avoid unexpectedly triggering this interrupt,
the default value of the FIFO_SAMPLES register is 0x80.
FIFO Ready
The FIFO_READY bit (Bit 1) is set when there is at least one
valid sample available in the FIFO output buffer. This bit is
cleared when no valid data is available in the FIFO.
Rev. B | Page 40 of 44
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