AD9834
TIMING CHARACTERISTICS
DVDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted.
Table 2.
Parameter
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8 MIN
t
8 MAX
t
9
t
10
t
11
t
11A
t
12
1
Limit at T
MIN
to T
MAX
20/13.33
8/6
8/6
25
10
10
5
10
t
4
− 5
5
3
8
8
5
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
MCLK period: 50 MHz/75 MHz
MCLK high duration: 50 MHz/75 MHz
MCLK low duration: 50 MHz/75 MHz
SCLK period
SCLK high duration
SCLK low duration
FSYNC-to-SCLK falling edge setup time
FSYNC-to-SCLK hold time
Data setup time
Data hold time
FSELECT, PSELECT setup time before MCLK rising edge
FSELECT, PSELECT setup time after MCLK rising edge
SCLK high to FSYNC falling edge setup time
Guaranteed by design, not production tested.
Timing Diagrams
t
1
MCLK
02705-003
t
2
t
3
Figure 3. Master Clock
MCLK
FSELECT,
PSELECT
VALID DATA
VALID DATA
VALID DATA
Figure 4. Control Timing
t
12
SCLK
t
5
t
7
t
6
t
4
t
8
FSYNC
t
9
SDATA
D15
D14
D2
t
10
D1
D0
D15
D14
02705-005
Figure 5. Serial Timing
Rev. C | Page 6 of 36
02705-004
t
11
t
11A
AD [ ANALOG DEVICES ]
