DAC8562
As with any analog system, it is recommended that the
DAC8562 power supply be bypassed on the same PC card that
contains the chip. Figure 10 shows the power supply rejection
versus frequency performance. This should be taken into ac-
count when using higher frequency switched-mode power sup-
plies with ripple frequencies of 100 kHz and higher.
TIMING AND CONTROL
The DAC8562 has a 12-bit DAC register that simplifies inter-
face to a 12-bit (or wider) data bus. The latch is controlled by
the Chip Enable (CE) input. If the application does not involve
a data bus, wiring CE low allows direct operation of the DAC.
The data latch is level triggered and acquires data from the data
bus during the time period when CE is low. When CE goes
high, the data is latched into the register and held until CE re-
turns low. The minimum time required for the data to be
present on the bus before CE returns high is called the data
setup time (tDS) as seen in Figure 2. The data hold time (tDH) is
the amount of time that the data has to remain on the bus after
CE goes high. The high speed timing offered by the DAC8562
provides for direct interface with no wait states in all but the
fastest microprocessors.
One advantage of the rail-to-rail output amplifier used in the
DAC8562 is the wide range of usable supply voltage. The part is
fully specified and tested over temperature for operation from
+4.75 V to +5.25 V. If reduced linearity and source current ca-
pability near full scale can be tolerated, operation of the
DAC8562 is possible down to +4.3 volts. The minimum operat-
ing supply voltage versus load current plot, in Figure 11, pro-
vides information for operation below VDD = +4.75 V.
Typical Performance Characteristics
5
100
80
V
T
= +5V
= +25°C
POS0
DD
V
= +5V
CURRENT0
60
DD
DATA = 000H
A
LIMIT0
4
40
RL TTIIEEDD TTOO AAGGNNDD
L
10
DA=TFAF=FHFFFH
20
3
2
DATA = 800H
0
T
= +85°C
R
TIED TO +2V
A
L
1
–20
–40
–60
T
= +25°C
A
0.1
0.01
1
0
R
TIED TO +5V
L
T
= –40°C
A
DATA = 000H
NEG
CURRENT
LIMIT
–80
–100
10
100
1k
10k
100k
1
1
2
3
10
100
1000
LOAD RESISTANCE – Ω
OUTPUT SINK CURRENT – µA
OUTPUT VOLTAGE – Volts
Figure 5. Output Swing vs. Load
Figure 6. Pull-Down Voltage vs.
Output Sink Current Capability
Figure 7. IOUT vs. VOUT
5
100
1ms
50mV
V
T
= +5V ±200mV AC
DD
= +25
V
T
= +5V
DD
°C
100
90
A
4
3
2
1
0
80
60
40
= +25°C
A
DATA = FFFH
10
T
= 25°C
0%
A
NBW = 630kHz
20
0
TIME = 1ms/DIV
0
1
2
3
4
5
10
100
1k
10k
100k
LOGIC VOLTAGE VALUE – Volts
FREQUENCY – Hz
Figure 10. Power Supply Rejection
vs. Frequency
Figure 8. Broadband Noise
Figure 9. Supply Current vs. Logic
Input Voltage
–6–
REV. A
ADI [ ADI ]
