DAC8562
As with any analog system, it is recommended that the
DAC8562 power supply be bypassed on the same PC card that
contains the chip. Figure 10 shows the power supply rejection
versus frequency performance. This should be taken into ac-
count when using higher frequency switched-mode power sup-
plies with ripple frequencies of 100 kHz and higher.
One advantage of the rail-to-rail output amplifier used in the
DAC8562 is the wide range of usable supply voltage. The part is
fully specified and tested over temperature for operation from
+4.75 V to +5.25 V. If reduced linearity and source current ca-
pability near full scale can be tolerated, operation of the
DAC8562 is possible down to +4.3 volts. The minimum operat-
ing supply voltage versus load current plot, in Figure 11, pro-
vides information for operation below V
DD
= +4.75 V.
TIMING AND CONTROL
The DAC8562 has a 12-bit DAC register that simplifies inter-
face to a 12-bit (or wider) data bus. The latch is controlled by
the Chip Enable (CE) input. If the application does not involve
a data bus, wiring
CE
low allows direct operation of the DAC.
The data latch is level triggered and acquires data from the data
bus during the time period when
CE
is low. When
CE
goes
high, the data is latched into the register and held until
CE
re-
turns low. The minimum time required for the data to be
present on the bus before
CE
returns high is called the data
setup time (t
DS
) as seen in Figure 2. The data hold time (t
DH
) is
the amount of time that the data has to remain on the bus after
CE
goes high. The high speed timing offered by the DAC8562
provides for direct interface with no wait states in all but the
fastest microprocessors.
Typical Performance Characteristics
5
OUTPUT PULLDOWN VOLTAGE – mV
V
DD
= +5V
T
A
= +25
°
C
100
V
DD
= +5V
DATA = 000H
10
OUTPUT CURRENT – mA
80
60
40
20
0
–20
–40
–60
–80
1
10
100
OUTPUT SINK CURRENT – µA
1000
–100
1
NEG
CURRENT
LIMIT
2
3
OUTPUT VOLTAGE – Volts
DATA = 800H
R
L
TIED TO +2V
POS0
CURRENT0
LIMIT0
OUTPUT VOLTAGE – Volts
4
R
L
TIED TO AGND
RL TIED TO AGND
DATA = FFFH
D = FFFH
3
1
T
A
= +85
°
C
2
T
A
= +25
°
C
0.1
T
A
= –40
°
C
1
R
L
TIED TO +5V
DATA = 000H
0
10
100
1k
10k
LOAD RESISTANCE –
Ω
100k
0.01
Figure 5. Output Swing vs. Load
Figure 6. Pull-Down Voltage vs.
Output Sink Current Capability
5
V
DD
= +5V
T
A
= +25
°
C
POWER SUPPLY REJECTION – dB
Figure 7. I
OUT
vs. V
OUT
OUTPUT NOISE VOLTAGE – 500µV/DIV
100
V
DD
= +5V ±200mV AC
80
T
A
= +25
°
C
DATA = FFFH
50mV
100
90
1ms
SUPPLY CURRENT – mA
4
3
60
2
40
10
0%
T
A
= 25°C
NBW = 630kHz
TIME = 1ms/DIV
1
20
0
0
1
2
3
4
LOGIC VOLTAGE VALUE – Volts
5
0
10
100
1k
10k
FREQUENCY – Hz
100k
Figure 8. Broadband Noise
Figure 9. Supply Current vs. Logic
Input Voltage
Figure 10. Power Supply Rejection
vs. Frequency
–6–
REV. A
AD [ ANALOG DEVICES ]
