DAC8562
WAFER TEST LIMITS (@ V = +5.0 V ؎ 5%, R = No Load, T = +25؇C, applies to part number DAC8562GBC only,
unless otherwise noted)
DD
L
A
Parameter
Symbol
Condition
Min
Typ
Max
Units
STATIC PERFORMANCE
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
Full-Scale Voltage
Reference Output Voltage
INL
DNL
VZSE
VFS
–1
–1
±3/4
±3/4
+1/2
4.095
2.500
+1
+ 1
+3
4.105
2.510
LSB
LSB
LSB
V
No Missing Codes
Data = 000H
Data = FFFH
4.085
2.490
VREF
V
LOGIC INPUTS
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
VIL
VIH
IIL
0.8
10
V
V
µA
2.4
SUPPLY CHARACTERISTICS
Positive Supply Current
IDD
VIH = 2.4 V, VIL = 0.8 V
3
6
mA
V
IL = 0 V, VDD = +5 V
VIH = 2.4 V, VIL = 0.8 V
IL = 0 V, VDD = +5 V
∆VDD = ±5%
0.6
15
3
1
30
5
mA
Power Dissipation
PDISS
PSS
mW
mW
%/%
V
Power Supply Sensitivity
0.002
0.004
NOTE
1Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
ABSOLUTE MAXIMUM RATINGS*
VDD to DGND and AGND . . . . . . . . . . . . . . . . –0.3 V, +10 V
Logic Inputs to DGND . . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
tCEW
1
CE
0
1
tDS
tDH
V
V
OUT to AGND . . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
REFOUT to AGND . . . . . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
DB
DATA VALID
11–0
0
1
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD
IOUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package Power Dissipation . . . . . . . . . . . . . .(TJ max – TA)/
tCLRW
CLR
JA
0
Thermal Resistance
JA
FS
±1 LSB
ERROR BAND
V
20-Pin Plastic DIP Package (P) . . . . . . . . . . . . . . . . 74°C/W
20-Lead SOIC Package (S) . . . . . . . . . . . . . . . . . . . 89°C/W
Maximum Junction Temperature (TJ max) . . . . . . . . . . 150°C
Operating Temperature Range . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C
OUT
ZS
tS
tS
Figure 2. Timing Diagram
Table I. Control Logic Truth Table
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CE
CLR
DAC Register Function
H
L
H
H
H
L
Latched
Transparent
Latched with New Data
Loaded with All Zeros
Latched All Zeros
↑
+
X
H
↑ +
↑
+ Positive Logic Transition; X Don't Care.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electrostatic
fields. Unused devices must be stored in conductive foam or shunts. The protective foam should be
discharged to the destination socket before devices are inserted.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–3–
ADI [ ADI ]
