ADV7300A/ADV7301A
TIMING SPECIFICATIONS
Parameter
MPU PORT
1
SCLOCK Frequency
SCLOCK High Pulsewidth, t
1
SCLOCK Low Pulsewidth, t
2
Hold Time (Start Condition), t
3
Setup Time (Start Condition), t
4
Data Setup Time, t
5
SDATA, SCLOCK Rise Time, t
6
SDATA, SCLOCK Fall Time, t
7
Setup Time (Stop Condition), t
8
RESET
Low Time
ANALOG OUTPUTS
Analog Output Delay
2
Output Skew
CLOCK CONTROL AND PIXEL PORT
3
f
CLK
f
CLK
Clock High Time, t
9
Clock Low Time, t
10
Data Setup Time, t
11
Data Hold Time, t
12
Output Access Time, t
13
Output Hold Time, t
14
Pipeline Delay
(V
AA
= V
DD
= 2.375 V–2.625 V, V
DD_IO
= 2.375 V–3.600 V, V
REF
= 1.235 V, R
SET
= 760
T
MIN
to T
MAX
(0 C to 70 C), unless otherwise noted.)
Min
0
0.6
1.3
0.6
0.6
100
300
300
0.6
100
8
1
27
81
40
40
2.0
2.0
14
4.0
61
62.5
66.5
33
43.5
36
Typ
Max
400
Unit
kHz
µs
µs
µs
µs
ns
ns
ns
µs
ns
ns
ns
MHz
MHz
% 1 clkcycle
% 1 clkcycle
ns
ns
ns
ns
clkcycles
clkcycles
clkcycles
clkcycles
clkcycles
clkcycles
, R
LOAD
= 150
,
Test Conditions
First Clock Generated after
This Period
Relevant for Repeated Start
Condition
Progressive Scan Mode
HDTV Mode/Async Mode
SD [2 ]
SD [8 ]
SD Component Filter [8 ]
PS [1 ], HD [1 ], Async
Timing Mode
PS [4 ]
HD [2 ]
NOTES
1
Guaranteed by characterization.
2
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.
3
Data: C[9:0]; S[9:0]; Y[9:0]
Control:
P_HSYNC; P_ VSYNC;
P_BLANK;
S_HSYNC; S_VSYNC; S_BLANK
Specifications subject to change without notice.
REV. A
–5–
AD [ ANALOG DEVICES ]
