ADV7300AKST 参数 Datasheet PDF下载

ADV7300A/ADV7301A

CLKIN_A

@ 27MHz

t

9

CONTROL

I/PS

S_HSYNC,

S_VSYNC,

S_BLANK

t

10

t

12

IN SLAVE

MODE

S9–S2

Y0

Y1

Y2

Y3

Y9–Y2

Cb0

Cr0

Cb2

Cr2

t

11

CONTROL

O/PS

S_HSYNC,

S_VSYNC

t

13

IN MASTER/SLAVE

MODE WITH

EAV/SAV

t

14

Figure 8. 16-Bit SD Pixel Input Timing Diagram, Input Mode: SD Input Only (Input Mode at Subaddress 01h = 000)

CLKIN_B

t

9

CONTROL

I/PS

P_HSYNC,

P_VSYNC,

P_BLANK

t

10

t

12

Y9–Y0

Y0

Y1

Y2

Y3

Y4

Y5

HD INPUT

C9–C0

Cb0

Cr0

Cb2

Cr2

Cb4

Cr4

t

11

CLKIN_A

CONTROL

I/PS

S_HSYNC,

S_VSYNC,

S_BLANK

S9–S0

t

9

t

10

t

12

SD INPUT

Cb0

Y0

Cr0

Y1

Cb1

Y2

t

11

Figure 9. SD and HD Simultaneous Input, Input Mode: SD and PS 20-Bit or SD and HDTV (Input Mode at

Subaddress 01h = 011, 101, or 110)

REV. A

–9–