ADV7180
VDP_VITC_MSKB, Address 0x50 [6], User Sub Map
0 (default)—Disables interrupt on VDP_VITC_Q signal.
1—Enables interrupt on VDP_VITC_Q signal.
Interrupt Status Register Details
•
Gemstar, PDC, VPS, or UTC: The user can select to
trigger an interrupt request each time sliced data is
available or to trigger an interrupt request only when
the sliced data has changed. Selection is made via the
GS_VPS_PDC_UTC_CB_ CHANGE bit.
The sequence for the interrupt-based reading of the VDP I2C
data registers is as follows for the CCAP standard:
The following read-only bits contain data detection information
from the VDP module since the status bit was last cleared or
unmasked.
1. User unmasks CCAP interrupt mask bit (0x50 Bit 0, User
Sub Map = 1). CCAP data occurs on the incoming video.
VDP slices CCAP data and places it into the VDP readback
registers.
2. The VDP CCAP AVAILABLE bit goes high, and the VDP
module signals to the interrupt controller to stimulate an
interrupt request (for CCAP in this case).
VDP_CCAPD_Q, Address 0x4E [0], User Sub Map
0 (default)—CCAP data has not been detected.
1—CCAP data has been detected.
VDP_CGMS_WSS_CHNGD_Q, Address 0x4E [2],
User Sub Map
3. The user reads the interrupt status bits (User Sub Map) and
sees that new CCAP data is available (0x4E Bit 0, User Sub
Map = 1).
0 (default)—CGMS or WSS data has not been detected.
1—CGM or WSS data has been detected.
4. The user writes 1 to the CCAP interrupt clear bit (0x4F
Bit 0, User Sub Map = 1) in the interrupt I2C space (this is a
self-clearing bit). This clears the interrupt on the INTRQ
pin but does not have an effect in the VDP I2C area.
5. The user reads the CCAP data from the VDP I2C area.
6. The user writes to Bit CC_CLEAR in the VDP_STATUS[0]
register, (0x78 Bit 0, User Sub Map = 1) to signify the CCAP
data has been read (therefore the VDP CCAP can be
updated at the next occurrence of CCAP).
VDP_GS_VPS_PDC_UTC_CHNG_Q, Address 0x4E [4],
User Sub Map
0 (default)—Gemstar, PDC, UTC, or VPS data has not been
detected.
1—Gemstar, PDC, UTC, or VPS data has been detected.
VDP_VITC_Q, Address 0x4E [6], User Sub Map,
Read Only
0 (default)—VITC data has not been detected.
1—VITC data has been detected.
7. Back to Step 2.
Interrupt Mask Register Details
Interrupt Status Clear Register Details
The following bits set the interrupt mask on the signal from the
VDP VBI data slicer.
It is not necessary to write 0 to these write-only bits because
they automatically reset after they have been set to 1 (self-
clearing).
VDP_CCAPD_MSKB, Address 0x50 [0], User Sub Map
0 (default)—Disables interrupt on VDP_CCAPD_Q signal.
1—Enables interrupt on VDP_CCAPD_Q signal.
VDP_CCAPD_CLR, Address 0x4F [0], User Sub Map
1—Clears VDP_CCAP_Q bit.
VDP_CGMS_WSS_CHNGD_MSKB, Address 0x50 [2],
User Sub Map
VDP_CGMS_WSS_CHNGD_CLR, Address 0x4F [2],
User Sub Map
0 (default)—Disables interrupt on VDP_CGMS_WSS_
CHNGD_Q signal.
1—Clears VDP_CGMS_WSS_CHNGD_Q bit.
VDP_GS_VPS_PDC_UTC_CHNG_CLR,
Address 0x4F [4], User Sub Map
1—Enables interrupt on VDP_CGMS_WSS_CHNGD_Q
signal.
1—Clears VDP_GS_VPS_PDC_UTC_CHNG_Q bit.
VDP_VITC_CLR, Address 0x4F [6], User Sub Map
1—Clears VDP_VITC_Q bit.
VDP_GS_VPS_PDC_UTC_CHNG_MSKB,
Address 0x50 [4], User Sub Map
0 (default)—Disables interrupt on
VDP_GS_VPS_PDC_UTC_CHNG_Q signal.
1—Enables interrupt on VDP_GS_VPS_PDC_UTC_CHNG_Q
signal.
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