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ADV7180BSTZ 参数 Datasheet PDF下载

ADV7180BSTZ图片预览
型号: ADV7180BSTZ
PDF下载: 下载PDF文件 查看货源
内容描述: 10位, 4倍过采样SDTV视频解码器 [10-Bit, 4 x Oversampling SDTV Video Decoder]
分类和应用: 解码器电视
文件页数/大小: 112 页 / 2178 K
品牌: ADI [ ADI ]
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ADV7180  
VITC  
VITC_CLEAR, VITC Clear, Address 0x78 [6],  
User Sub Map, Write Only, Self-Clearing  
VITC has a sequence of 10 syncs in between each data byte.  
The VDP strips these syncs from the data stream to output  
only the data bytes. The VITC results are available in Register  
VDP_VITC_DATA_0 to Register VDP_VITC_DATA_8  
(Register 0x92 to Register 0x9A, User Sub Map).  
1—Reinitializes the VITC readback registers.  
VITC_AVL, VITC Available, Address 0x78 [6],  
User Sub Map  
0—VITC data was not detected.  
1—VITC data was detected.  
The VITC has a CRC byte at the end; the syncs in between each  
data byte are also used in this CRC calculation. Because the  
syncs in between each data byte are not output, the CRC is  
calculated internally. The calculated CRC is available for the  
user in the VITC_CALC_CRC register (Resister 0x9B, User Sub  
Map). Once the VDP completes decoding the VITC line, the  
VITC_DATA and VITC_CALC_CRC registers are updated and  
the VITC_AVL bit is set.  
VITC Readback Registers  
See Figure 46 for the I2C to VITC bit mapping.  
TO  
VITC WAVEFORM  
BIT0, BIT1  
BIT88, BIT89  
Figure 46. VITC Waveform and Decoded Data Correlation  
Table 79. VITC Readback Registers1  
Signal Name  
Register Location  
Address (User Sub Map)  
VITC_DATA_0[7:0]  
VITC_DATA_1[7:0]  
VITC_DATA_2[7:0]  
VITC_DATA_3[7:0]  
VITC_DATA_4[7:0]  
VITC_DATA_5[7:0]  
VITC_DATA_6[7:0]  
VITC_DATA_7[7:0]  
VITC_DATA_8[7:0]  
VITC_CALC_CRC[7:0]  
VDP_VITC_DATA_0[7:0] (VITC Bits [9:2])  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
0x92  
0x93  
0x94  
0x95  
0x96  
0x97  
0x98  
0x99  
0x9A  
0x9B  
VDP_VITC_DATA_1[7:0] (VITC Bits [19:12])  
VDP_VITC_DATA_2[7:0] (VITC Bits [29:22])  
VDP_VITC_DATA_3[7:0] (VITC Bits [39:32])  
VDP_VITC_DATA_4[7:0] (VITC Bits [49:42])  
VDP_VITC_DATA_5[7:0] (VITC Bits [59:52])  
VDP_VITC_DATA_6[7:0] (VITC Bits [69:62])  
VDP_VITC_DATA_7[7:0] (VITC Bits [79:72])  
VDP_VITC_DATA_8[7:0] (VITC Bits [89:82])  
VDP_VITC_CALC_CRC[7:0]  
1 The register is a readback register; default value does not apply.  
Rev. A | Page 62 of 112