Data Sheet
ADV7180
Bit (Shading Indicates
Default State)
User Sub Map
Bit Description
Address Register
7
6
5
4
3
2
1
0
Comments
Notes
0x4A
Interrupt Status 3
(read only)
SD_OP_CHNG_Q; SD 60 Hz/50 Hz
frame rate at output
0
No change in SD signal standard
detected at the output
These bits can be cleared
and masked by
Register 0x4B and
Register 0x4C, respectively
1
A change in SD signal standard is
detected at the output
SD_V_LOCK_CHNG_Q
SD_H_LOCK_CHNG_Q
0
1
No change in SD VSYNC lock status
SD VSYNC lock status has changed
No change in HSYNC lock status
SD HSYNC lock status has changed
0
1
SD_AD_CHNG_Q; SD autodetect
changed
0
1
No change in AD_RESULT[2:0] bits in
Status 1 register
AD_RESULT[2:0] bits in Status 1 register
have changed
SCM_LOCK_CHNG_Q; SECAM lock
PAL_SW_LK_CHNG_Q
0
1
No change in SECAM lock status
SECAM lock status has changed
0
1
No change in PAL swinging burst
lock status
PAL swinging burst lock status has
changed
Reserved
x
x
x
x
x
x
Not used
0x4B
0x4C
0x4E
Interrupt Clear 3
(write only)
SD_OP_CHNG_CLR
0
1
Do not clear
Clears SD_OP_CHNG_Q bit
Do not clear
SD_V_LOCK_CHNG_CLR
SD_H_LOCK_CHNG_CLR
SD_AD_CHNG_CLR
0
1
Clears SD_V_LOCK_CHNG_Q bit
Do not clear
0
1
Clears SD_H_LOCK_CHNG_Q bit
Do not clear
0
1
Clears SD_AD_CHNG_Q bit
Do not clear
SCM_LOCK_CHNG_CLR
PAL_SW_LK_CHNG_CLR
0
1
Clears SCM_LOCK_CHNG_Q bit
Do not clear
0
1
Clears PAL_SW_LK_CHNG_Q bit
Not used
Reserved
Interrupt Mask 3
(read/write)
SD_OP_CHNG_MSK
0
1
Masks SD_OP_CHNG_Q bit
Unmasks SD_OP_CHNG_Q bit
Masks SD_V_LOCK_CHNG_Q bit
Unmasks SD_V_LOCK_CHNG_Q bit
Masks SD_H_LOCK_CHNG_Q bit
Unmasks SD_H_LOCK_CHNG_Q bit
Masks SD_AD_CHNG_Q bit
Unmasks SD_AD_CHNG_Q bit
Masks SCM_LOCK_CHNG_Q bit
Unmasks SCM_LOCK_CHNG_Q bit
Masks PAL_SW_LK_CHNG_Q bit
Unmasks PAL_SW_LK_CHNG_Q bit
Not used
SD_V_LOCK_CHNG_MSK
SD_H_LOCK_CHNG_MSK
SD_AD_CHNG_MSK
SCM_LOCK_CHNG_MSK
PAL_SW_LK_CHNG_MSK
Reserved
0
1
0
1
0
1
0
1
0
1
Interrupt Status 4 (read only) VDP_CCAPD_Q
0
1
Closed captioning not detected
Closed captioning detected
These bits can be cleared
and masked by Register
0x4F and Register 0x50,
respectively; note that an
interrupt in Register 0x4E
for the CCAP, Gemstar,
CGMS, WSS, VPS, PDC,
UTC, and VITC data uses
the VDP data slicer
Reserved
x
VDP_CGMS_WSS_CHNGD_Q; see
0x9C Bit 4 of user sub map to determine
whether interrupt is issued for a
change in detected data or for when
data is detected regardless of content
0
1
CGMS/WSS data is not changed/
not available
CGMS/WSS data is changed/available
Reserved
x
VDP_GS_VPS_PDC_UTC_CHNG_Q;
see 0x9C Bit 5 of User Sub Map to deter-
mine whether interrupt is issued for a
change in detected data or for when
data is detected regardless of content
0
1
Gemstar/PDC/VPS/UTC data is not
changed/not available
Gemstar/PDC/VPS/UTC data is
changed/available
Reserved
x
VDP_VITC_Q
0
1
VITC data is not available in the VDP
VITC data is available in the VDP
Reserved
x
Rev. G | Page 101 of 120
ADI [ ADI ]
