Data Sheet
ADV7180
Table 108. Register Map Descriptions (Interrupt Operation)1, 2
Bit (Shading Indicates
Default State)
User Sub Map
Bit Description
Address Register
0x40 Interrupt Configuration 1
7
6
5
4
3
2
1
0
0
1
1
0
0
1
0
1
Comments
Notes
INTRQ_OP_SEL[1:0]; interrupt
drive level select
Open drain
Drive low when active
Drive high when active
Reserved
MPU_STIM_INTRQ; manual
interrupt set mode
0
1
Manual interrupt mode disabled
Manual interrupt mode enabled
Not used
Reserved
x
MV_INTRQ_SEL[1:0];
Macrovision interrupt select
0
0
1
1
0
1
0
1
Reserved
Pseudo sync only
Color stripe only
Pseudo sync or color stripe
Three XTAL periods
15 XTAL periods
63 XTAL periods
Active until cleared
No change
INTRQ_DUR_SEL[1:0];
interrupt duration select
0
0
1
1
0
1
0
1
0x42
Interrupt Status 1
(read only)
SD_LOCK_Q
0
1
These bits can be cleared
or masked in Register 0x43
and Register 0x44, res-
pectively
SD input has caused the decoder to go
from an unlocked state to a locked state
SD_UNLOCK_Q
0
1
No change
SD input has caused the decoder to go
from a locked state to an unlocked state
Reserved
x
x
x
SD_FR_CHNG_Q
0
1
No change
Denotes a change in the free-run status
No change
MV_PS_CS_Q
0
1
Pseudo sync/color striping detected;
see Register 0x40 MV_INTRQ_SEL[1:0]
for selection
Reserved
x
x
x
0x43
Interrupt Clear 1
(write only)
SD_LOCK_CLR
0
1
Do not clear
Clears SD_LOCK_Q bit
Do not clear
SD_UNLOCK_CLR
0
1
Clears SD_UNLOCK_Q bit
Not used
Reserved
0 0 0
SD_FR_CHNG_CLR
0
1
Do not clear
Clears SD_FR_CHNG_Q bit
Do not clear
MV_PS_CS_CLR
0
1
Clears MV_PS_CS_Q bit
Not used
Reserved
0x44
Interrupt Mask 1
(read/write)
SD_LOCK_MSK
0
1
Masks SD_LOCK_Q bit
Unmasks SD_LOCK_Q bit
Masks SD_UNLOCK_Q bit
Unmasks SD_UNLOCK_Q bit
Not used
SD_UNLOCK_MSK
0
1
Reserved
0 0 0
SD_FR_CHNG_MSK
0
1
Masks SD_FR_CHNG_Q bit
Unmasks SD_FR_CHNG_Q bit
Masks MV_PS_CS_Q bit
Unmasks MV_PS_CS_Q bit
Not used
MV_PS_CS_MSK
Reserved
0
1
Rev. G | Page 99 of 120
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