ADV7180
Data Sheet
Bit (Shading Indicates
Default State)
User Sub Map
Bit Description
Address Register
7
6
5
4
3
2
1
0
Comments
Notes
0x45
Raw Status 2
(read only)
CCAPD
0
No CCAPD data detected—
VBI System 2
These bits are status
bits only; they cannot be
cleared or masked;
Register 0x46 is used for
this purpose
1
CCAPD data detected—VBI System 2
Reserved
x
x
x
EVEN_FIELD
0
1
Current SD field is odd numbered
Current SD field is even numbered
Reserved
x
x
MPU_STIM_INTRQ
0
1
MPU_STIM_INTRQ = 0
MPU_STIM_INTRQ = 1
0x46
Interrupt Status 2
(read only)
CCAPD_Q
GEMD_Q
0
1
Closed captioning not detected in the
input video signal—VBI System 2
These bits can be cleared
or masked by Register 0x47
and Register 0x48, res-
pectively; note that the
interrupt in Register 0x46
for the CCAP, Gemstar,
CGMS, and WSS data uses
the Mode 1 data slicer
Closed captioning data detected in the
video input signal—VBI System 2
0
1
Gemstar data not detected in the input
video signal—VBI System 2
Gemstar data detected in the input
video signal—VBI System 2
Reserved
x
x
SD_FIELD_CHNGD_Q
0
1
SD signal has not changed field from
odd to even or vice versa
SD signal has changed Field from odd to
even or vice versa
Reserved
x
Not used
Reserved
x
x
0
Not used
MPU_STIM_INTRQ_Q
0
1
Manual interrupt not set
Manual interrupt set
Do not clear—VBI System 2
Clears CCAPD_Q bit—VBI System 2
Do not clear
0x47
0x48
0x49
Interrupt Clear 2
(write only)
CCAPD_CLR
GEMD_CLR
0
1
Note that interrupt in
Register 0x46 for the
CCAP, Gemstar, CGMS,
and WSS data uses the
Mode 1 data slicer
0
1
Clears GEMD_Q bit
Reserved
0 0
SD_FIELD_CHNGD_CLR
0
1
Do not clear
Clears SD_FIELD_CHNGD_Q bit
Not used
Reserved
x
MPU_STIM_INTRQ_CLR
0
1
Do not clear
Clears MPU_STIM_INTRQ_Q bit
Masks CCAPD_Q bit—VBI System 2
Unmasks CCAPD_Q bit—VBI System 2
Masks GEMD_Q bit—VBI System 2
Unmasks GEMD_Q bit—VBI System 2
Not used
Interrupt Mask 2
(read/write)
CCAPD_MSK
GEMD_MSK
0
1
Note that interrupt in
Register 0x46 for the
CCAP, Gemstar, CGMS,
and WSS data uses the
Mode 1 data slicer
0
1
Reserved
0 0
SD_FIELD_CHNGD_MSK
0
1
Masks SD_FIELD_CHNGD_Q bit
Unmasks SD_FIELD_CHNGD_Q bit
Not used
Reserved
0
MPU_STIM_INTRQ_MSK
0
1
Masks MPU_STIM_INTRQ_Q bit
Unmasks MPU_STIM_INTRQ_Q bit
SD 60 Hz signal output
Raw Status 3
(read only)
SD_OP_50Hz; SD 60 Hz/50 Hz
frame rate at output
0
1
These bits are status
bits only; they cannot be
cleared or masked;
Register 0x4A is used for
this purpose
SD 50 Hz signal output
SD_V_LOCK
0
1
SD vertical sync lock not established
SD vertical sync lock established
SD horizontal sync lock not established
SD horizontal sync lock established
Not used
SD_H_LOCK
0
1
Reserved
x
SCM_LOCK
0
1
SECAM lock not established
SECAM lock established
Not used
Reserved
x
x
x
Rev. G | Page 100 of 120
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