ADV7175A/ADV7176A
CLOCK
COMPOSITE
VIDEO
e.g., VCR
SCRESET/RTC
VIDEO
DECODER
(e.g., ADV7185)
GREEN/LUMA/Y
RED/CHROMA/V
M
U
X
OR CABLE
P7–P0
BLUE/COMPOSITE/U
COMPOSITE
MPEG
DECODER
HSYNC
FIELD/VSYNC
ADV7175A/ADV7176A
SEQUENCE
RESERVED
2
BIT
H/LTRANSITION
COUNT START
RESET
4 BITS
RESERVED
5 BITS
RESERVED
3
BIT
LOW
14 BITS
RESERVED
128
1
FSCPLL INCREMENT
0
0
13
21
RTC
TIME SLOT: 01
6768
14
19
NOT USED IN
ADV7175A/ADV7176A
VALID
SAMPLE SAMPLE
INVALID
8/LLC
NOTES:
1
F
PLL INCREMENT IS 22 BITS LONG, VALUED LOADED INTO ADV7175A/ADV7176A FSC DDS REGISTER IS
PLL INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUB CARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD
SC
F
SC
BE WRITTEN TO THE SUB CARRIER FREQUENCY REGISTERS OF THE ADV7175A/ADV7176A.
2
SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE.
3
RESET BIT
RESET ADV7175A/ADV7176A’s DDS.
Figure 13. RTC Tim ing and Connections
Ver tical Blanking D ata Inser tion
It is possible to allow encoding of incoming YCbCr data on those lines of VBI that do not bear line sync or pre/post-equalization
pulses (see Figures 15 to 26). T his mode of operation is called “Partial Blanking” and is selected by setting MR31 to 1. It allows the
insertion of any VBI data (Opened VBI) into the encoded output waveform. T his data is present in digitized incoming YCbCr data
stream (e.g., WSS data, CGMS, VPS, etc.). Alternatively, the entire VBI may be blanked (no VBI data inserted) on these lines by
setting MR31 to 0.
T he complete VBI comprises of the following lines:
525/60 Systems, Lines 525 to 21 for Field 1 and Lines 262 to Line 284 for Field 2.
625/50 Systems, Lines 624 to Line 22 and Lines 311 to 335.
T he “Opened VBI” consists of:
525/60 Systems, Lines 10 to 21 for Field 1 and second half of Line 273 to Line 284 for Field 2.
625/50 Systems, Line 7 to Line 22 and Lines 319 to 335.
Mode 0 (CCIR-656): Slave O ption
(T iming Register 0 T R0 = X X X X X 0 0 0)
T he ADV7175A/ADV7176A is controlled by the SAV (Start Active Video) and EAV (End Active Video) time codes in the pixel
data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately
before and after each line during active picture and retrace. Mode 0 is illustrated in Figure 14. T he HSYNC, FIELD/VSYNC and
BLANK (if not used) pins should be tied high during this mode.
–14–
REV. B
ADI [ ADI ]
