ADV7175A/ADV7176A
PIN FUNCTION DESCRIPTIONS
Pin
No.
1, 11, 20,
28, 30
10, 19, 21,
29, 43
15
16
Mnemonic
V
AA
GND
HSYNC
FIELD/VSYNC
Input/
Output
P
G
I/O
I/O
Function
Power Supply (+3 V to +5 V).
Ground Pin.
HSYNC
(Modes 1 and 2) Control Signal. This pin may be configured to
output (Master Mode) or accept (Slave Mode) Sync signals.
Dual Function FIELD (Mode 1) and
VSYNC
(Mode 2) Control Signal. This
pin may be configured to output (Master Mode) or accept (Slave Mode)
these control signals.
Video Blanking Control Signal. The pixel inputs are ignored when this is
logic level “0.” This signal is optional.
TTL Address Input. This signal sets up the LSB of the MPU address.
The input resets the on chip timing generator and sets the ADV7175A/
ADV7176A into default mode. This is NTSC operation, Timing Slave Mode
0, 8-bit operation, 2
×
composite and S-Video out and all DACs powered on.
MPU Port Serial Interface Clock Input.
MPU Port Serial Data Input/Output.
Compensation Pin. Connect a 0.1
µF
capacitor from COMP to V
AA
. For
Optimum Dynamic Performance in Low Power Mode, the value of the
COMP capacitor can be lowered to as low as 2.2 nF.
RED/S-Video C/V Analog Output.
GREEN/S-Video Y/Y Analog Output.
BLUE/Composite/U Analog Output.
PAL/NTSC Composite Video Output. Full-Scale Output is 180IRE (1286
mV) for NTSC and 1300 mV for PAL.
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
A 150
Ω
resistor connected from this pin to GND is used to control full-scale
amplitudes of the video signals.
This pin can be configured as an input by setting MR22 and MR21 of Mode
Register 2. It can be configured as a subcarrier reset pin, in which case a high
to low transition on this pin will reset the subcarrier to Field 0. Alternatively
it may be configured as a Real Time Control (RTC) input.
Teletext Data Request Signal/Defaults to GND when Teletext not selected
(enables backward compatibility to ADV7175/ADV7176).
Teletext Data/Defaults to V
AA
when Teletext not selected (enables backward
compatibility to ADV7175/ADV7176).
8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0) or
16-Bit YCrCb Pixel Port (P0–P15). P0 represents the LSB.
TTL Clock Input. Requires a stable 27 MHz reference Clock for standard
operation. Alternatively, a 24.52 MHz (NTSC) or 29.5 MHz (PAL) can be
used for square pixel operation.
17
18
22
BLANK
ALSB
RESET
I/O
I
I
23
24
25
SCLOCK
SDATA
COMP
I
I/O
O
26
27
31
32
33
34
35
DAC C
DAC D
DAC B
DAC A
V
REF
R
SET
SCRESET/RTC
O
O
O
O
I/O
I
I
36
37
38–42
2–9, 12–14
44
TTXREQ/GND
TTX/V
AA
P0–P15
CLOCK
O
I
I
I
–10–
REV. B
AD [ ANALOG DEVICES ]
