ADV7175A/ADV7176A
0
–10
–20
SUBCARRIER RESET
T ogether with the SCRESET /RT C PIN and Bits MR22 and
MR21 of Mode Register 2, the ADV7175A/ADV7176A can be
used in subcarrier reset mode. T he subcarrier will reset to
Field 0 at the start of the following field when a low to high
transition occurs on this input pin.
–30
–40
–50
–60
REAL TIME CO NTRO L
T ogether with the SCRESET /RT C PIN and Bits MR22 and
MR21 of Mode Register 2, the ADV7175A/ADV7176A can be
used to lock to an external video source. T he real time control
mode allows the ADV7175A/ADV7176A to automatically alter
the subcarrier frequency to compensate for line length variation.
When the part is connected to a device that outputs a digital
datastream in the RT C format (such as an ADV7185 video
decoder [see Figure 13]), the part will automatically change to
the compensated subcarrier frequency on a line by line basis.
T his digital datastream is 67 bits wide and the subcarrier is
contained in Bits 0 to 21. Each bit is two clock cycles long.
00HEX should be written to all four subcarrier frequency regis-
ters when using this mode.
0
2
4
6
8
10
12
FREQUENCY – MHz
Figure 12. PAL UV Filter
CO LO R BAR GENERATIO N
T he ADV7175A/ADV7176A can be configured to generate
75% amplitude, 75% saturation (75/7.5/75/7.5) for NT SC or
75% amplitude, 100% saturation (100/0/75/0) for PAL color
bars. T hese are enabled by setting MR17 of Mode Register 1 to
Logic “1.”
VID EO TIMING D ESCRIP TIO N
T he ADV7175A/ADV7176A is intended to interface to off-
the-shelf MPEG1 and MPEG2 Decoders. Consequently, the
ADV7175A/ADV7176A accepts 4:2:2 YCrCb Pixel Data via a
CCIR-656 pixel port and has several video timing modes of
operation that allow it to be configured as either system master
video timing generator or a slave to the system video timing
generator. T he ADV7175A/ADV7176A generates all of the
required horizontal and vertical timing periods and levels for the
analog video outputs.
SQ UARE P IXEL MO D E
T he ADV7175A/ADV7176A can be used to operate in square
pixel mode. For NT SC operation an input clock of 24.5454
MHz is required. Alternatively an input clock of 29.5 MHz is
required for PAL operation. T he internal timing logic adjusts
accordingly for square pixel mode operation.
CO LO R SIGNAL CO NTRO L
T he color information can be switched on and off the video
output using Bit MR24 of Mode Register 2.
T he ADV7175A/ADV7176A calculates the width and place-
ment of analog sync pulses, blanking levels and color burst
envelopes. Color bursts are disabled on appropriate lines, and
serration and equalization pulses are inserted where required.
BURST SIGNAL CO NTRO L
T he burst information can be switched on and off the video
output using Bit MR25 of Mode Register 2.
In addition the ADV7175A/ADV7176A supports a PAL or
NT SC square pixel operation in slave mode. T he part requires
an input pixel clock of 24.5454 MHz for NT SC and an input
pixel clock of 29.5 MHz for PAL. T he internal horizontal line
counters place the various video waveform sections in the cor-
rect location for the new clock frequencies.
NTSC P ED ESTAL CO NTRO L
T he pedestal on both odd and even fields can be controlled on a
line by line basis using the NT SC Pedestal Control Registers.
T his allows the pedestals to be controlled during the vertical
blanking interval (Lines 10 to 25 and Lines 273 to 288).
T he ADV7175A/ADV7176A has four distinct master and four
distinct slave timing configurations. T iming Control is estab-
lished with the bidirectional SYNC, BLANK and FIELD/
VSYNC pins. T iming Mode Register 1 can also be used to vary
the timing pulsewidths and where they occur in relation to each
other.
P IXEL TIMING D ESCRIP TIO N
The ADV7175A/ADV7176A can operate in either 8-bit or
16-bit YCrCb Mode.
8-Bit YCr Cb Mode
T his default mode accepts multiplexed YCrCb inputs through
the P7-P0 pixel inputs. T he inputs follow the sequence Cb0, Y0
Cr0, Y1 Cb1, Y2, etc. T he Y, Cb and Cr data are input on a
rising clock edge.
16-Bit YCr Cb Mode
T his mode accepts Y inputs through the P7–P0 pixel inputs and
multiplexed CrCb inputs through the P15–P8 pixel inputs. T he
data is loaded on every second rising edge of CLOCK. The inputs
follow the sequence Cb0, Y0 Cr0, Y1 Cb1, Y2, etc.
REV. B
–13–
ADI [ ADI ]
