ADV7175A/ADV7176A
ANALOG
VIDEO
EAV CODE
INPUT PIXELS
Y
C
F 0 0 X 8 1 8 1
Y
r
F 0 0 Y 0 0 0 0
0 F F A A A
0 F F B B B
ANCILLARY DATA
(HANC)
268 CLOCK
4 CLOCK
280 CLOCK
END OF ACTIVE
VIDEO LINE
SAV CODE
C
C
8 1 8 1 F 0 0 X C Y C Y C
Y r Y b
b
0 0 0 0 F 0 0 Y b
r
NTSC/PAL M SYSTEM
(525 LlNES/60Hz)
PAL SYSTEM
(625 LINES/50Hz)
4 CLOCK
4 CLOCK
1440 CLOCK
4 CLOCK
1440 CLCOK
START OF ACTIVE
VIDEO LINE
Figure 14. Timing Mode 0 (Slave Mode)
Mode 0 (CCIR-656): Master Option
(Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7175A/ADV7176A generates H, V and F signals required for the SAV (Start Active Video) and EAV (End Active Video)
time codes in the CCIR-656 standard. The H bit is output on the
HSYNC
pin, the V bit is output on the
BLANK
pin, and the F bit
is output on the FIELD/VSYNC pin. Mode 0 is illustrated in Figure 15 (NTSC) and Figure 16 (PAL). The H, V and F transitions
relative to the video waveform are illustrated in Figure 17.
DISPLAY
VERTICAL BLANK
DISPLAY
522
H
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
V
F
EVEN FIELD
ODD FIELD
DISPLAY
VERTICAL BLANK
DISPLAY
260
H
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
V
F
ODD FIELD
EVEN FIELD
Figure 15. Timing Mode 0 (NTSC Master Mode)
REV. B
–15–
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