ADV7170/ADV7171
REGISTER ACCESSES
The ADV7170/ADV7171 act as standard slave devices on the
bus. The data on the SDATA pin is eight bits long, supporting
The MPU can write to or read from all of the ADV7170/
ADV7171 registers except the subaddress register, which is a
write-only register. The subaddress register determines which
register the next read or write operation accesses. All commu-
nications with the part through the bus start with an access to
the subaddress register. A read/write operation is performed
from/to the target address, which then increments to the next
address until a stop command on the bus is performed.
RW
the 7-bit addresses plus the R/
bit. The ADV7170 has 48
subaddresses, and the ADV7171 has 26 subaddresses to enable
access to the internal registers. It therefore interprets the first
byte as the device address and the second byte as the starting
subaddress. The subaddresses’ auto-increment allows data to be
written to or read from the starting subaddress. A data transfer
is always terminated by a stop condition. The user can also
access any unique subaddress register on a one-by-one basis
without having to update all the registers. There is one
exception. The subcarrier frequency registers should be updated
in sequence, starting with Subcarrier Frequency Register 0. The
auto-increment function should then be used to increment and
access Subcarrier Frequency Register 1, Subcarrier Frequency
Register 2, and Subcarrier Frequency Register 3. The subcarrier
frequency registers should not be accessed independently.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of
sequence with normal read and write operations, they cause an
immediate jump to the idle condition. During a given SCLOCK
high period, the user should issue only one start condition, one
stop condition, or a single stop condition followed by a single
start condition. If an invalid subaddress is issued by the user,
the ADV7170/ADV7171 do not issue an acknowledge, and they
return to the idle condition. If in auto-increment mode the user
exceeds the highest subaddress, the following action is taken:
In read mode, the highest subaddress register contents
continue to be output until the master device issues a no-
acknowledge. This indicates the end of a read. A no-
acknowledge condition is where the SDATA line is not pulled
low on the ninth pulse.
In write mode, the data for the invalid byte is not loaded into
any subaddress register, a no-acknowledge is issued by the
ADV7170/ADV7171, and the part returns to the idle
condition.
Figure 35 illustrates an example of data transfer for a read
sequence and the start and stop conditions.
Figure 36 shows bus write and read sequences.
SDATA
SCLOCK
S
P
9
1–7
9
9
1–7
8
8
1–7
8
START ADDR R/W ACK SUBADDRESS ACK
DATA
ACK
STOP
Figure 35. Bus Data Transfer
Rev. C | Page 27 of 64
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