ADV7170/ADV7171
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
6
7
5
21
22
23
HSYNC
BLANK
VSYNC
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
318
319
320
335
336
317
334
HSYNC
BLANK
VSYNC
ODD FIELD
EVEN FIELD
Figure 28. Timing Mode 2 (PAL)
Mode 2: Master Option HSYNC, VSYNC, BLANK
(Timing Register 0 TR0 = X X X X X 1 0 1)
HSYNC
In this mode the ADV7170/ADV7171 can generate horizontal and vertical SYNC signals. A coincident low transition of both
and
is high indicates the start of an even field. The
input is disabled, the ADV7170/ADV7171 automatically blank all normally blank lines as
HSYNC BLANK VSYNC
VSYNC
BLANK
VSYNC
HSYNC
low transition when
inputs indicates the start of an odd field. A
BLANK
signal is optional. When the
per CCIR-624. Mode 2 is shown in Figure 27 (NTSC) and Figure 28 (PAL). Figure 29 shows the
,
, and
VSYNC
for an odd-to-even field
for an
HSYNC BLANK
, and
even-to-odd field transition relative to the pixel data. Figure 30 shows the
transition relative to the pixel data.
,
HSYNC
VSYNC
PAL = 12 × CLOCK/2
NTSC = 16 × CLOCK/2
BLANK
PIXEL
DATA
Cb
Y
Cr
Y
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Figure 29. Timing Mode 2 Even-to-Odd Field Transition Master/Slave
HSYNC
VSYNC
PAL = 864 × CLOCK/2
NTSC = 858 × CLOCK/2
PAL = 12 × CLOCK/2
NTSC = 16 × CLOCK/2
BLANK
PIXEL
DATA
Cb
Y
Cr
Y
Cb
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Figure 30. Timing Mode 2 Odd-to-Even Field Transition Master/Slave
Rev. C | Page 24 of 64
ADI [ ADI ]
