ADV7170/ADV7171
Mode 1: Master Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 0 1 1)
In this mode the ADV7170/ADV7171 can generate horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input when
HSYNC BLANK BLANK
is low indicates a new frame, that is, vertical retrace. The
signal is optional. When the
input is disabled, the
ADV7170/ADV7171 automatically blank all normally blank lines as per CCIR-624. Pixel data is latched on the rising clock edge following
HSYNC BLANK
, and
the timing signal transitions. Mode 1 is shown in Figure 24 (NTSC) and Figure 25 (PAL). Figure 26 illustrates the
FIELD for an odd or even field transition relative to the pixel data.
,
HSYNC
FIELD
PAL = 12 × CLOCK/2
NTSC = 16 × CLOCK/2
BLANK
PIXEL
Cr
Y
Cb
Y
DATA
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Figure 26. Timing Mode 1 Odd/Even Field Transitions Master/Slave
Mode 2: Slave Option HSYNC, VSYNC, BLANK
(Timing Register 0 TR0 = X X X X X 1 0 0)
HSYNC
In this mode the ADV7170/ADV7171 accept horizontal and vertical SYNC signals. A coincident low transition of both
and
is high indicates the start of an even field. The
input is disabled, the ADV7170/ADV7171 automatically blank all normally blank lines as
VSYNC
BLANK
VSYNC
HSYNC
low transition when
inputs indicates the start of an odd field. A
BLANK
signal is optional. When the
per CCIR-624. Mode 2 is illustrated in Figure 27 (NTSC) and Figure 28 (PAL).
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
20
21
22
1
2
3
4
6
7
8
10
11
5
9
HSYNC
BLANK
VSYNC
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
283
285
284
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
HSYNC
BLANK
VSYNC
EVEN FIELD
ODD FIELD
Figure 27. Timing Mode 2 (NTSC)
Rev. C | Page 23 of 64
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