Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Table 9. SPI Slave Mode Timing (Phase Mode = 0)
Parameter
Description
CS to SCLK edge1
Min
Typ
Max
Unit
tCS
(2 × tHCLK) + (2 × tUCLK
)
ns
tSL
tSH
tDAV
tDSU
tDHD
tDF
tDR
tSR
tSF
tDOCS
tSFS
SCLK low pulse width2
(SPIDIV + 1) × tHCLK
(SPIDIV + 1) × tHCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK high pulse width2
Data output valid after SCLK edge
Data input setup time before SCLK edge1
Data input hold time after SCLK edge1
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
Data output valid after CS edge
CS high after SCLK edge
25
1 × tUCLK
2 × tUCLK
5
5
5
5
12.5
12.5
12.5
12.5
25
0
1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider; see Figure 67.
2 tHCLK depends on the clock divider or CD bits in the POWCONMMR. tHCLK = tUCLK/2CD; see Figure 67.
CS
tCS
tSFS
SCLK
(POLARITY = 0)
tSH
tSL
tSF
tSR
SCLK
(POLARITY = 1)
tDAV
tDOCS
tDF
tDR
MISO
MOSI
MSB
BITS 6 TO 1
LSB
MSB IN
BITS 6 TO 1
LSB IN
tDSU
tDHD
Figure 18. SPI Slave Mode Timing (Phase Mode = 0)
Rev. F | Page 19 of 104
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