Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Table 4. I2C Timing in Fast Mode (400 kHz)
Slave
Max
Master
Typ
Parameter
Description
Min
200
100
300
100
0
100
100
1.3
Unit
ns
ns
ns
ns
ns
ns
ns
s
ns
ns
ns
tL
tH
SCL low pulse width1
1360
1140
SCL high pulse width1
Start condition hold time
Data setup time
tSHD
tDSU
tDHD
tRSU
tPSU
tBUF
tR
740
400
Data hold time
Setup time for repeated start
Stop condition setup time
Bus-free time between a stop condition and a start condition
Rise time for both SCL and SDA
Fall time for both SCL and SDA
Pulse width of spike suppressed
400
200
300
300
50
tF
tSUP
1 tHCLK depends on the clock divider or CD bits in the POWCON MMR. tHCLK = tUCLK/2CD; see Figure 67.
Table 5. I2C Timing in Standard Mode (100 kHz)
Slave
Master
Typ
Parameter
Description
Min
Max
Unit
μs
ns
μs
ns
μs
μs
μs
μs
μs
ns
tL
tH
SCL low pulse width1
4.7
4.0
4.0
250
0
4.7
4.0
4.7
SCL high pulse width1
Start condition hold time
Data setup time
tSHD
tDSU
tDHD
tRSU
tPSU
tBUF
tR
Data hold time
3.45
Setup time for repeated start
Stop condition setup time
Bus-free time between a stop condition and a start condition
Rise time for both SCL and SDA
Fall time for both SCL and SDA
1
300
tF
1 tHCLK depends on the clock divider or CD bits in the POWCON MMR. tHCLK = tUCLK/2CD; see Figure 67.
tBUF
tSUP
tR
MSB
tF
SDA (I/O)
MSB
LSB
ACK
tDSU
tDSU
tDHD
tDHD
tPSU
tR
tSHD
tRSU
tH
1
2–7
8
9
1
SCL (I)
tL
tSUP
P
S
S(R)
tF
STOP
START
REPEATED
START
CONDITION CONDITION
Figure 14. I2C Compatible Interface Timing
Rev. F | Page 15 of 104
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