ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Table 3. External Memory Read Cycle
Parameter
CLK1
Min
Typ
Max
Unit
1/MD clock
ns typ × (POWCON[2:0] + 1)
tMS_AFTER_CLKH
tADDR_AFTER_CLKH
tAE_H_AFTER_MS
tAE
tHOLD_ADDR_AFTER_AE_L
tRD_L_AFTER_AE_L
tRD_H_AFTER_CLKH
tRD
4
4
8
16
ns
ns
½ CLK
(XMxPAR[14:12] + 1) × CLK
½ CLK + (! XMxPAR[10] ) × CLK
½ CLK + (! XMxPAR[10]+ ! XMxPAR[9] ) × CLK
0
4
(XMxPAR[3:0] + 1) × CLK
tDATA_BEFORE_RD_H
tDATA_AFTER_RD_H
tRELEASE_MS_AFTER_RD_H
16
8
ns
+ (! XMxPAR[9]) × CLK
1 × CLK
1 See Table 78.
CLK
ECLK
MSx
tMS_AFTER_CLKH
tAE_H_AFTER_MS
tRELEASE_MS_AFTER_RD_H
tAE
tRD_L_AFTER_AE_L
AE
WS
tRD
tRD_H_AFTER_CLKH
RS
tDATA_BEFORE_RD_H
tDATA_AFTER_RD_H
tADDR_AFTER_CLKH
AD[16:1] FFFF
2348
XXXX CDEF XX
234A
XX
89AB
tHOLD_ADDR_AFTER_AE_L
BHE
BLE
A16
Figure 13. External Memory Read Cycle (See Table 78)
Rev. F | Page 14 of 104
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