ADSP-BF531/ADSP-BF532/ADSP-BF533
Serial Ports
through
and
through
describe Serial Port operations.
Table 21. Serial Ports—External Clock
Parameter
Timing Requirements
t
SFSE
TFS/RFS Setup Before TSCLK/RSCLK
1
t
HFSE
TFS/RFS Hold After TSCLK/RSCLK
1
t
SDRE
Receive Data Setup Before RSCLK
1
t
HDRE
Receive Data Hold After RSCLK
1
TSCLK/RSCLK Width
t
SCLKEW
t
SCLKE
TSCLK/RSCLK Period
1
Min
3.0
3.0
3.0
3.0
4.5
15.0
Max
Unit
ns
ns
ns
ns
ns
ns
Referenced to sample edge.
Table 22. Serial Ports—Internal Clock
Parameter
Timing Requirements
t
SFSI
TFS/RFS Setup Before TSCLK/RSCLK
1
t
HFSI
TFS/RFS Hold After TSCLK/RSCLK
1
t
SDRI
Receive Data Setup Before RSCLK
1
t
HDRI
Receive Data Hold After RSCLK
1
t
SCLKEW
TSCLK/RSCLK Width
t
SCLKE
TSCLK/RSCLK Period
1
Min
8.0
–2.0
6.0
0.0
4.5
15.0
Max
Unit
ns
ns
ns
ns
ns
ns
Referenced to sample edge.
Table 23. Serial Ports—External Clock
Parameter
Switching Characteristics
t
DFSE
TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)
1
t
HOFSE
TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)
1
t
DDTE
Transmit Data Delay After TSCLK
1
Transmit Data Hold After TSCLK
1
t
HDTE
1
Min
Max
10.0
Unit
ns
ns
ns
ns
0.0
10.0
0.0
Referenced to drive edge.
Table 24. Serial Ports—Internal Clock
Parameter
Switching Characteristics
t
DFS
I
TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)
1
TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)
1
t
HOFS
I
t
DDT
I
Transmit Data Delay After TSCLK
1
t
HDT
I
Transmit Data Hold After TSCLK
1
t
SCLKIW
TSCLK/RSCLK Width
1
Min
Max
3.0
Unit
ns
ns
ns
ns
ns
−1.0
3.0
−2.0
4.5
Referenced to drive edge.
Rev. 0 |
Page 28 of 56 | March 2004
AD [ ANALOG DEVICES ]
