ADSP-BF531/ADSP-BF532/ADSP-BF533
Parallel Peripheral Interface Timing
Table 20
and
describe Parallel Peripheral
Interface operations.
Table 20. Parallel Peripheral Interface Timing
Parameter
Timing Requirements
t
PCLKW
PPI_CLK Width
t
PCLK
PPI_CLK Period
1
t
SFSPE
External Frame Sync Setup Before PPI_CLK
t
HFSPE
External Frame Sync Hold After PPI_CLK
Receive Data Setup Before PPI_CLK
t
SDRPE
t
HDRPE
Receive Data Hold After PPI_CLK
Switching Characteristics - GP Output and Frame Capture Modes
t
DFSPE
Internal Frame Sync Delay After PPI_CLK
t
HOFSPE
Internal Frame Sync Hold After PPI_CLK
t
DDTPE
Transmit Data Delay After PPI_CLK
Transmit Data Hold After PPI_CLK
t
HDTPE
1
Min
6.0
15.0
3.0
3.0
2.0
4.0
Max
Unit
ns
ns
ns
ns
ns
ns
10.0
0.0
10.0
0.0
ns
ns
ns
ns
PPI_CLK frequency cannot exceed f
SCLK
/2
DRIVE
EDGE
SAMPLE
EDGE
t
PCLKW
PPI_CLK
t
DFSPE
t
HOFSPE
PPI_FS1
PPI_FS2
t
SFSPE
t
HFSPE
t
DDTPE
t
HDTPE
PPIx
t
SDRPE
t
HDRPE
Figure 15. GP Output Mode and Frame Capture Timing
Rev. 0 |
Page 27 of 56 | March 2004
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