ADSP-BF531/ADSP-BF532/ADSP-BF533
SDRAM Interface Timing
Table 18. SDRAM Interface Timing
1
Parameter
Timing Requirements
t
SSDAT
DATA Setup Before CLKOUT
t
HSDAT
DATA Hold After CLKOUT
Switching Characteristics
t
SCLK
CLKOUT Period
t
SCLKH
CLKOUT Width High
t
SCLKL
CLKOUT Width Low
Command, ADDR, Data Delay After CLKOUT
2
t
DCAD
t
HCAD
Command, ADDR, Data Hold After CLKOUT
1
t
DSDAT
Data Disable After CLKOUT
t
ENSDAT
Data Enable After CLKOUT
1
2
Min
2.1
0.8
7.5
2.5
2.5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
6.0
0.8
6.0
1.0
For V
DDINT
= 1.2 V.
Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
t
SCLK
CLKOUT
t
SCLKH
t
SSDAT
t
HSDAT
DATA (IN)
t
SCLKL
t
DCAD
t
ENSDAT
DATA(OUT)
t
D SDA T
t
HCAD
t
DCAD
CMND ADDR
(OUT)
t
HCAD
NOTE: COMMAND =
SRAS, SCAS, SWE,
SDQM,
SMS,
SA10, SCKE.
Figure 13. SDRAM Interface Timing
Rev. 0 |
Page 25 of 56 | March 2004
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