ADSP-BF531/ADSP-BF532/ADSP-BF533
RISE AND FALL TIME ns (10% to 90%)
plus the various output disable times as specified in the
(for example t
DSDAT
for an SDRAM
write cycle as shown in
14
12
RISE TIME
10
8
FALL TIME
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see
V
LOAD
is 0.95 V for V
DDEXT
(nominal) = 1.8 V or 1.5 V for V
DDEXT
(nominal) =
2.5 V/3.3 V.
through
show how
output rise time varies with capacitance. The delay and hold
specifications given should be derated by a factor derived from
these figures. The graphs in these figures may not be linear out
side the ranges shown.
TO
OUTPUT
PIN
30pF
50�½
V
LOAD
6
4
2
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 46. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver A at V
DDEXT
= 2.25 V
12
RISE AND FALL TIME ns (10% to 90%)
Figure 44. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
16
14
RISE AND FALL TIME ns (10% to 90%)
RISE TIME
12
10
FALL TIME
8
6
4
2
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
10
RISE TIME
8
FALL TIME
6
4
2
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 47. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver A at V
DDEXT
= 3.65 V
14
Figure 45. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver A at V
DDEXT
= 1.75 V
RISE AND FALL TIME ns (10% to 90%)
12
RISE TIME
10
8
FALL TIME
6
4
2
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 48. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver B at V
DDEXT
= 1.75 V
Rev. E |
Page 46 of 60 |
July 2007
AD [ ANALOG DEVICES ]
