ADSP-BF531/ADSP-BF532/ADSP-BF533
TIMING SPECIFICATIONS
through
describe the timing requirements for
the ADSP-BF531/ADSP-BF532/ADSP-BF533 processor clocks.
Take care in selecting MSEL, SSEL, and CSEL ratios so as not to
exceed the maximum core clock and system clock as described
Table 12. Core Clock (CCLK) Requirements—400 MHz Models
1
T
JUNCTION
= 125°C
Max
400
333
295
All
2
Other T
JUNCTION
Max
400
364
333
280
250
in
and the voltage con
trolled oscillator (VCO) operating frequencies described in
describes phase-locked loop operating
conditions.
Parameter
f
CCLK
CCLK Frequency (V
DDINT
=1.14 V Minimum)
f
CCLK
CCLK Frequency (V
DDINT
=1.045 V Minimum)
f
CCLK
CCLK Frequency (V
DDINT
=0.95 V Minimum)
f
CCLK
CCLK Frequency (V
DDINT
=0.85 V Minimum)
f
CCLK
CCLK Frequency (V
DDINT
=0.8 V Minimum)
1
2
Internal Regulator Setting
1.20 V
1.10 V
1.00 V
0.90 V
0.85 V
Unit
MHz
MHz
MHz
MHz
MHz
See
See
Table 13. Core Clock (CCLK) Requirements—500 MHz, 533 MHz, and 600 MHz Models
Parameter
f
CCLK
CCLK Frequency (V
DDINT
=1.3 V Minimum)
1
f
CCLK
CCLK Frequency (V
DDINT
=1.2 V Minimum)
2
CCLK Frequency (V
DDINT
=1.14 V Minimum)
3
f
CCLK
f
CCLK
CCLK Frequency (V
DDINT
=1.045 V Minimum)
f
CCLK
CCLK Frequency (V
DDINT
=0.95 V Minimum)
f
CCLK
CCLK Frequency (V
DDINT
=0.85 V Minimum)
f
CCLK
CCLK Frequency (V
DDINT
=0.8 V Minimum)
1
2
Internal Regulator Setting
1.30 V
1.25 V
1.20 V
1.10 V
1.00 V
0.90 V
0.85 V
Max
600
533
500
444
400
333
250
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Applies to 600 MHz models only. See
Applies to 533 MHz and 600 MHz models only. See
533 MHz models cannot support internal regulator levels above 1.25 V.
3
Applies to 500 MHz, 533 MHz, and 600 MHz models. See
500 MHz models cannot support internal regulator levels above 1.20 V.
Table 14. Phase-Locked Loop Operating Conditions
Parameter
f
VCO
Voltage Controlled Oscillator (VCO) Frequency
Min
50
Max
Maximum f
CCLK
Unit
MHz
Table 15. System Clock (SCLK) Requirements
1
Parameter
MBGA/PBGA
f
SCLK
f
SCLK
LQFP
f
SCLK
f
SCLK
1
V
DDEXT
= 1.8 V
Max
CLKOUT/SCLK Frequency (V
DDINT
≥
1.14 V)
CLKOUT/SCLK Frequency (V
DDINT
<
1.14 V)
CLKOUT/SCLK Frequency (V
DDINT
≥
1.14 V)
CLKOUT/SCLK Frequency (V
DDINT
<
1.14 V)
100
100
100
83
V
DDEXT
= 2.5 V/3.3 V
Max
133
100
133
83
Unit
MHz
MHz
MHz
MHz
t
SCLK
(= 1/f
SCLK
) must be greater than or equal to t
CCLK
.
Rev. E |
Page 24 of 60 |
July 2007
AD [ ANALOG DEVICES ]
