ADSP-BF531/ADSP-BF532/ADSP-BF533
JTAG Test and Emulation Port Timing
and
describe JTAG port operations.
Table 30. JTAG Port Timing
V
DDEXT
= 1.8 V
Min
Max
20
4
4
4
5
4
10
12
V
DDEXT
= 2.5 V/3.3 V
Min
Max
20
4
4
4
5
4
10
12
Parameter
Timing Requirements
t
TCK
TCK Period
TDI, TMS Setup Before TCK High
t
STAP
t
HTAP
TDI, TMS Hold After TCK High
t
SSYS
System Inputs Setup Before TCK High
1
t
HSYS
System Inputs Hold After TCK High
1
t
TRSTW
TRST Pulse Width
2
(Measured in TCK Cycles)
Switching Characteristics
t
DTDO
TDO Delay from TCK Low
t
DSYS
System Outputs Delay After TCK Low
3
1
Unit
ns
ns
ns
ns
ns
TCK
ns
ns
0
0
System Inputs = DATA15–0, ARDY, TMR2–0, PF15–0, PPI_CLK, RSCLK0–1, RFS0–1, DR0PRI, DR0SEC, TSCLK0–1, TFS0–1, DR1PRI, DR1SEC, MOSI, MISO, SCK, RX,
RESET, NMI, BMODE1–0, BR, PP3–0.
2
50 MHz maximum
3
System Outputs = DATA15–0, ADDR19–1, ABE1–0, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, TMR2–0, PF15–0, RSCLK0–1, RFS0–1,
TSCLK0–1, TFS0–1, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MOSI, MISO, SCK, TX, BG, BGH, PPI3–0.
t
TCK
TCK
t
STAP
TMS
TDI
t
HTAP
t
DTDO
TDO
t
SSYS
SYSTEM
INPUTS
t
HSYS
t
DSYS
SYSTEM
OUTPUT
Figure 29. JTAG Port Timing
Rev. E |
Page 42 of 60 |
July 2007
AD [ ANALOG DEVICES ]
