ADSP-BF531/ADSP-BF532/ADSP-BF533
DATA RECEIVE—INTERNAL CLOCK
DRIVE
EDGE
SAMPLE
EDGE
DATA RECEIVE—EXTERNAL CLOCK
DRIVE
EDGE
SAMPLE
EDGE
t
SCLKIW
RSCLKx
RSCLKx
t
SCLKEW
t
DFSI
t
HOFSI
RFSx
t
DFSE
t
SFSI
t
HFSI
RFSx
t
HOFSE
t
SFSE
t
HFSE
t
SDRI
DRx
t
HDRI
DRx
t
SDRE
t
HDRE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RSCLKx OR TSCLKx CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT—INTERNAL CLOCK
DRIVE
EDGE
SAMPLE
EDGE
DATA TRANSMIT—EXTERNAL CLOCK
DRIVE
EDGE
SAMPLE
EDGE
t
SCLKIW
TSCLKx
TSCLKx
t
SCLKEW
t
DFSI
t
HOFSI
TFSx
t
DFSE
t
SFSI
t
HFSI
TFSx
t
HOFSE
t
SFSE
t
HFSE
t
DDTI
t
HDTI
DTx
DTx
t
DDTE
t
HDTE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RSCLKx OR TSCLKx CAN BE USED AS THE ACTIVE SAMPLING EDGE.
Figure 22. Serial Ports
Table 24. Serial Ports—Enable and Three-State
V
DDEXT
= 1.8 V
Min
Max
0
10.0
−2.0
3.0
−2.0
3.0
V
DDEXT
= 2.5 V/3.3 V
Min
Max
Unit
0
10.0
ns
ns
ns
ns
Parameter
Switching Characteristics
t
DTENE
Data Enable Delay from External TSCLKx
1
t
DDTTE
Data Disable Delay from External TSCLKx
t
DTENI
Data Enable Delay from Internal TSCLKx
t
DDTTI
Data Disable Delay from Internal TSCLKx
1
Referenced to drive edge.
Table 25. External Late Frame Sync
V
DDEXT
= 1.8 V
V
DDEXT
= 1.8 V
LQFP/PBGA Packages
MBGA Package
Min
Max
Min
Max
10.5
0
10.0
0
V
DDEXT
= 2.5 V/3.3 V
All Packages
Min
Max
10.0
Parameter
Switching Characteristics
t
DDTLFSE
Data Delay from Late External TFSx or External RFSx
with MCE = 1, MFD = 0
1, 2
t
DTENLFS
Data Enable from Late FS or MCE = 1, MFD = 0
1, 2
0
1
2
Unit
ns
ns
MCE = 1, TFSx enable and TFSx valid follow t
DTENLFS
and t
DDTLFSE
.
If external RFSx/TFSx setup to RSCLKx/TSCLK x> t
SCLKE
/2, then t
DD
T
TE
/
I
and t
DTENE
/
I
apply; otherwise t
DDTLFSE
and t
DTENLFS
apply.
Rev. E |
Page 35 of 60 |
July 2007
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