ADSP-BF531/ADSP-BF532/ADSP-BF533
Serial Peripheral Interface (SPI) Port
—Master Timing
and
describe SPI port master operations.
Table 26. Serial Peripheral Interface (SPI) Port—Master Timing
V
DDEXT
= 1.8 V
V
DDEXT
= 1.8 V
LQFP/PBGA Packages
MBGA Package
Min
Max
Min
Max
8.5
–1.5
2t
SCLK
–1.5
2t
SCLK
–1.5
2t
SCLK
–1.5
4t
SCLK
–1.5
2t
SCLK
–1.5
2t
SCLK
–1.5
0
–1.0
V
DDEXT
= 2.5 V/3.3 V
All Packages
Min
Max
7.5
–1.5
2t
SCLK
–1.5
2t
SCLK
–1.5
2t
SCLK
–1.5
4t
SCLK
–1.5
2t
SCLK
–1.5
2t
SCLK
–1.5
0
–1.0
Parameter
Timing Requirements
t
SSPIDM
Data Input Valid to SCK Edge (Data Input Setup) 10.5
t
HSPIDM
SCK Sampling Edge to Data Input Invalid
–1.5
Switching Characteristics
t
SDSCIM
SPISELx Low to First SCK Edge
2t
SCLK
–1.5
t
SPICHM
Serial Clock High Period
2t
SCLK
–1.5
t
SPICLM
Serial Clock Low Period
2t
SCLK
–1.5
t
SPICLK
Serial Clock Period
4t
SCLK
–1.5
t
HDSM
Last SCK Edge to SPISELx High
2t
SCLK
–1.5
t
SPITDM
Sequential Transfer Delay
2t
SCLK
–1.5
0
t
DDSPIDM
SCK Edge to Data Out Valid (Data Out Delay)
t
HDSPIDM
SCK Edge to Data Out Invalid (Data Out Hold) –1.0
SPISELx
(OUTPUT)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
+4.0
6
+4.0
6
+4.0
t
SDSCIM
SCK
(CPOL = 0)
(OUTPUT)
t
SPICHM
t
SPICLM
t
SPICLK
t
HDSM
t
SPITDM
t
SPICLM
SCK
(CPOL = 1)
(OUTPUT)
t
SPICHM
t
DDSPIDM
MOSI
(OUTPUT)
CPHA = 1
MISO
(INPUT)
MSB
t
HDSPIDM
LSB
t
SSPIDM
MSB VALID
t
HSPIDM
t
SSPIDM
LSB VALID
t
HSPIDM
t
DDSPIDM
MOSI
(OUTPUT)
CPHA = 0
MSB
t
HDSPIDM
LSB
t
SSPIDM
MISO
(INPUT)
MSB VALID
t
HSPIDM
LSB VALID
Figure 24. Serial Peripheral Interface (SPI) Port—Master Timing
Rev. E |
Page 37 of 60 |
July 2007
AD [ ANALOG DEVICES ]
