ADSP-BF531/ADSP-BF532
External Port Bus Request and Grant Cycle Timing
Table 19 and Figure 14 describe external port bus request and
bus grant operations.
Table 19. External Port Bus Request and Grant Cycle Timing
VDDEXT = 1.8 V VDDEXT = 2.5 V/3.3 V
Parameter
Min Max Min
Max
Unit
Timing Requirements
tBS
tBH
BR Asserted to CLKOUT High Setup
4.6
1.0
4.6
0.0
ns
ns
CLKOUT High to BR Deasserted Hold Time
Switching Characteristics
tSD
CLKOUT Low to xMS, Address, and RD/WR Disable
4.5
4.5
4.6
4.6
4.6
4.6
4.5
4.5
3.6
3.6
3.6
3.6
ns
ns
ns
ns
ns
ns
tSE
CLKOUT Low to xMS, Address, and RD/WR Enable
CLKOUT High to BG High Setup
tDBG
tEBG
tDBH
tEBH
CLKOUT High to BG Deasserted Hold Time
CLKOUT High to BGH High Setup
CLKOUT High to BGH Deasserted Hold Time
CLKOUT
tBH
tBS
BR
tSD
tSE
AMSx
tSD
tSE
ADDR19-1
ABE1-0
tSD
tSE
AWE
ARE
tDBG
tEBG
BG
tDBH
tEBH
BGH
Figure 14. External Port Bus Request and Grant Cycle Timing
Rev. D
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Page 28 of 60
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August 2006
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