ADSP-BF531/ADSP-BF532
Clock and Reset Timing
Table 15 and Figure 10 describe clock and reset operations. Per
Absolute Maximum Ratings on Page 22, combinations of
CLKIN and clock multipliers must not select core/peripheral
clocks in excess of 400 MHz/133 MHz.
Table 15. Clock and Reset Timing
Parameter
Min
Max
Unit
Timing Requirements
tCKIN
CLKIN Period
25.0
100.01
ns
ns
ns
ns
tCKINL
tCKINH
tWRST
CLKIN Low Pulse2
CLKIN High Pulse1
RESET Asserted Pulse Width Low3
10.0
10.0
11 tCKIN
1 If DF bit in PLL_CTL register is set, then the maximum tCKIN period is 50 ns.
2 Applies to bypass mode and nonbypass mode.
3 Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2,000 CLKIN cycles, while RESET is asserted,
assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator).
tCKIN
CLKIN
tCKINL
tCKINH
tWRST
RESET
Figure 10. Clock and Reset Timing
Rev. D
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Page 24 of 60
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August 2006
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