ADSP-BF531/ADSP-BF532
Serial Ports
Table 21 on Page 32 through Table 24 on Page 33 and Figure 19
on Page 34 through Figure 21 on Page 36 describe Serial Port
operations.
Table 21. Serial Ports—External Clock
VDDEXT = 1.8 V VDDEXT = 2.5 V/3.3 V
Parameter
Min Max Min
Max
Unit
Timing Requirements
tSFSE
tHFSE
tSDRE
tHDRE
TFS/RFS Setup Before TSCLK/RSCLK1
TFS/RFS Hold After TSCLK/RSCLK1
Receive Data Setup Before RSCLK1
Receive Data Hold After RSCLK1
3.0
3.0
3.0
3.0
4.5
15.0
3.0
3.0
3.0
3.0
4.5
15.0
ns
ns
ns
ns
ns
ns
tSCLKEW TSCLK/RSCLK Width
tSCLKE TSCLK/RSCLK Period
Switching Characteristics
tDFSE
tHOFSE
tDDTE
tHDTE
TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)2
TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)1
Transmit Data Delay After TSCLK1
10.0
10.0
10.0
10.0
ns
ns
ns
ns
0.0
0.0
0.0
0.0
Transmit Data Hold After TSCLK1
1 Referenced to sample edge.
2 Referenced to drive edge.
Table 22. Serial Ports—Internal Clock
VDDEXT = 1.8 V VDDEXT = 2.5 V/3.3 V
Parameter
Min Max Min
Max
Unit
Timing Requirements
tSFSI
tHFSI
tSDRI
tHDRI
TFS/RFS Setup Before TSCLK/RSCLK1
TFS/RFS Hold After TSCLK/RSCLK1
Receive Data Setup Before RSCLK1
Receive Data Hold After RSCLK1
11.0
−2.0
9.0
9.0
ns
ns
ns
ns
ns
ns
−2.0
9.0
0.0
0.0
tSCLKEW TSCLK/RSCLK Width
tSCLKE TSCLK/RSCLK Period
Switching Characteristics
4.5
4.5
15.0
15.0
tDFSI
TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)2
TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)1
Transmit Data Delay After TSCLK1
3.0
3.0
3.0
3.0
ns
ns
ns
ns
ns
tHOFSI
tDDTI
tHDTI
−1.0
−1.0
Transmit Data Hold After TSCLK1
−2.0
−2.0
tSCLKIW TSCLK/RSCLK Width
4.5
4.5
1 Referenced to sample edge.
2 Referenced to drive edge.
Rev. D
|
Page 32 of 60
|
August 2006
ADI [ ADI ]
