ADSP-BF531/ADSP-BF532
Asynchronous Memory Read Cycle Timing
Table 16. Asynchronous Memory Read Cycle Timing
VDDEXT = 1.8 V VDDEXT = 2.5 V/3.3 V
Parameter
Min Max Min
Max
Unit
Timing Requirements
tSDAT
DATA15–0 Setup Before CLKOUT
DATA15–0 Hold After CLKOUT
ARDY Setup Before CLKOUT
ARDY Hold After CLKOUT
2.1
1.0
4.0
1.0
2.1
0.8
4.0
0.0
ns
ns
ns
ns
tHDAT
tSARDY
tHARDY
Switching Characteristics
tDO
tHO
Output Delay After CLKOUT1
Output Hold After CLKOUT 1
6.0
6.0
ns
ns
1.0
0.8
1 Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
HOLD
1 CYCLE
SETUP
2 CYCLES
PROGRAMMED READ ACCESS
4 CYCLES
ACCESS EXTENDED
3 CYCLES
CLKOUT
tDO
tHO
AMSx
ABE1–0
ABE, ADDRESS
ADDR19–1
AOE
tDO
tHO
ARE
tHARDY
tSARDY
tHARDY
ARDY
tSARDY
tSDAT
tHDAT
DATA15–0
READ
Figure 11. Asynchronous Memory Read Cycle Timing
Rev. D
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Page 25 of 60
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August 2006
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