ADSP-BF531/ADSP-BF532
TIMING SPECIFICATIONS
Table 12 through Table 14 describe the timing requirements for
the ADSP-BF531/ADSP-BF532 processor clocks. Take care in
selecting MSEL, SSEL, and CSEL ratios so as not to exceed the
maximum core clock and system clock as described in Absolute
Maximum Ratings on Page 22, and the voltage controlled oscil-
lator (VCO) operating frequencies described in Table 13.
Table 13 describes phase-locked loop operating conditions.
Table 12. Core Clock Requirements
TJUNCTION = 125°C
Max
All1 Other TJUNCTION
Max
Parameter
Min
2.50
3.00
3.39
Min
2.50
2.75
3.00
3.57
4.00
Unit
ns
tCCLK Core Cycle Period (VDDINT =1.14 V minimum)
tCCLK Core Cycle Period (VDDINT =1.045 V minimum)
tCCLK Core Cycle Period (VDDINT =0.95 V minimum)
tCCLK Core Cycle Period (VDDINT =0.85 V minimum)
tCCLK Core Cycle Period (VDDINT =0.8 V )
1 See Operating Conditions on Page 20.
ns
ns
ns
ns
Table 13. Phase-Locked Loop Operating Conditions
Parameter
Min
Max
Unit
fVCO Voltage Controlled Oscillator (VCO) Frequency
50
Maximum fCCLK
MHz
Table 14. Maximum SCLK Conditions
Parameter1
VDDEXT = 1.8 V
VDDEXT = 2.5 V
VDDEXT = 3.3 V
Unit
MBGA/PBGA
fSCLK
CLKOUT/SCLK Frequency (VDDINT ≥ 1.14 V)
CLKOUT/SCLK Frequency (VDDINT < 1.14 V)
100
100
133
100
133
100
MHz
MHz
fSCLK
LQFP
fSCLK
CLKOUT/SCLK Frequency (VDDINT ≥ 1.14 V)
CLKOUT/SCLK Frequency (VDDINT < 1.14 V)
100
83
133
83
133
83
MHz
MHz
fSCLK
1 tSCLK (= 1/fSCLK) must be greater than or equal to tCCLK
.
Rev. D
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Page 23 of 60
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August 2006
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