ADSP-BF531WBBZ-4A 参数 Datasheet PDF下载

ADSP-BF531/ADSP-BF532/ADSP-BF533

Timer Cycle Timing

and

describe timer expired operations. The

input signal is asynchronous in width capture mode and exter­

nal clock mode and has an absolute maximum input frequency

of f

SCLK

/2 MHz.

Table 29. Timer Cycle Timing

V

DDEXT

= 1.8 V

Min

Max

1

1

1

(2

32

–1)

V

DDEXT

= 2.5 V/3.3 V

Min

Max

1

1

1

(2

32

–1)

Parameter

Timing Characteristics

t

WL

Timer Pulse Width Input Low

1

(Measured in SCLK Cycles)

t

WH

Timer Pulse Width Input High

(Measured in SCLK Cycles)

Switching Characteristic

t

HTO

Timer Pulse Width Output

2

(Measured in SCLK Cycles)

1

2

Unit

SCLK

SCLK

SCLK

The minimum pulse widths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in PWM output mode.

The minimum time for t

HTO

is one cycle, and the maximum time for t

HTO

equals (2

32

–1) cycles.

CLKOUT

t

HTO

TMRx

(PWM OUTPUT MODE)

TMRx

(WIDTH CAPTURE AND

EXTERNAL CLOCK MODES)

t

WL

t

WH

Figure 28. Timer PWM_OUT Cycle Timing

Rev. E |

Page 41 of 60 |

July 2007